Staff Design Engineer, HBM Architecture

Job Title

Staff Design Engineer, HBM Architecture

Role Summary

The HBM Architecture team architects datapath and micro-architecture for High Bandwidth Memory (HBM) logic and core dies. This role defines and implements high-speed datapath circuitry to meet bandwidth, power, reliability, and manufacturability targets for next-generation HBM products.

Work includes close collaboration with PHY, ECC, verification, layout, and system teams from concept through silicon bring-up and production.

Experience Level

Senior / Staff-level. Typical qualification: Bachelor's degree with 7+ years of relevant industry experience, or a Master’s degree with 5+ years.

Responsibilities

Design, document, and deliver datapath architectures and implementations for HBM products.

• Architect and design HBM read and write datapath across logic and core die: alignment, buffering, timing, and control logic.
• Develop high-speed, low-latency datapath circuits for multi-channel HBM and wide internal buses.
• Optimize datapath designs for bandwidth, power, area, and timing closure at advanced process nodes.
• Design and integrate data reliability features such as parity, ECC hooks, lane redundancy, and remapping mechanisms.
• Drive schematic-level and RTL-level datapath implementations, including clocking, gating, and reset strategies.
• Collaborate with PHY, DFT, verification, and layout teams to ensure functionality, testability, and manufacturability.
• Contribute to design reviews, documentation, silicon bring-up, and technical mentoring across programs.
• Apply approved AI-enabled tools to improve productivity, streamline workflows, and accelerate problem solving.

Requirements

Core technical must-haves and relevant hands-on experience.

• 3+ years experience in high-speed digital datapath design (memory, SerDes, or SoC datapath).
• 3+ years hands-on experience with digital schematic build, RTL, or mixed-signal datapath implementations.
• Proven ability to optimize designs for timing closure, bandwidth, power, and area at advanced nodes.
• Experience designing and integrating data-reliability mechanisms into datapaths.
• Experience working cross-functionally with PHY, verification, layout, and DFT teams.
• Experience with clocking strategies, clock gating, and reset design in datapaths.
• Strong problem-solving skills, technical documentation, and effective cross-team communication.
• Nice-to-have: deep understanding of HBM/DRAM architectures, layout/floorplanning, static timing analysis (STA), timing-closure methodologies, and advanced-node signal-integrity and skew control techniques.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field with 7+ years of relevant industry experience; or a Master's degree with 5+ years of relevant industry experience. No certifications or alternative-equivalent education language were specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.