Staff ASIC Verification Engineer

Job Title

Staff ASIC Verification Engineer

Role Summary

Join the ASIC verification team to develop and execute verification for storage and compute data‑center ASICs. The role works closely with RTL designers and software teams to validate chip functionality across simulation and lab environments.

Experience Level

Senior (Staff-level). Years of experience: not specified.

Responsibilities

Primary responsibilities include planning and executing verification activities from block to chip level and driving debug to closure.

• Review specifications, architectures, and micro‑architectures with the design team.
• Define test plans and verification strategies.
• Develop block‑level and chip‑level verification environments and testbenches.
• Generate and analyze functional and code coverage metrics.
• Run regressions and debug/triage failures in simulation environments.
• Validate features in the lab and collaborate with software teams to reproduce and resolve issues.

Requirements

Required technical skills and tools for the role.

• Proficiency with UVM, constrained‑random and coverage‑driven verification methodologies.
• Strong SystemVerilog and Verilog experience and testbench development for verification.
• Familiarity with Verilog simulators and waveform viewers.
• Strong debug skills and experience with debug tools (e.g., Verdi).
• Scripting experience (Perl, Python) for testbench automation and flow development.
• Experience creating and running regression suites and producing verification metrics.
• Nice-to-have: knowledge of C/C++.

Education Requirements

BSEE, MSEE or above (Electrical Engineering).

About the Company

Company: ScaleFlux

Headquarters: Milpitas, CA, United States

ScaleFlux designs computational storage SSDs and related software for enterprise, cloud and data center applications. Their technology offloads processing into the storage device to accelerate databases, analytics and other data-intensive workloads.