Staff ASIC Verification Engineer

Job Title

Staff ASIC Verification Engineer

Role Summary

The Staff ASIC Verification Engineer will lead SoC and IP-level verification efforts on the ASIC Verification team, focusing on verification strategy, test plan definition, testbench architecture, and execution to support successful tape-out.

The role requires close collaboration with design and project stakeholders to improve testability, debug testbenches, and harmonize verification methodologies across projects.

Experience Level

Senior-level. See Education Requirements for stated degree and experience equivalencies.

Responsibilities

Primary responsibilities include defining verification approach, delivering verification environments, and driving signoff with coverage metrics.

• Define SoC verification strategies, test plans, and execution plans with the ASIC Verification team.
• Own IP-level ASIC verification efforts toward SoC tape-out.
• Design and deliver testbench architectures, functional models, test environments, and test suites to meet coverage targets.
• Implement and harmonize verification methodologies and industry best practices across the organization.
• Collaborate with design teams and stakeholders on testability improvements and debug during testbench bring-up.
• Support gate-level verification and lab validation activities; coordinate FPGA emulation when required.

Requirements

Must-have technical skills and experience.

• Proven track record in verification strategy development and execution for large SoCs with signoff using coverage metrics.
• Hands-on experience with UVM methodology and SystemVerilog.
• Proficiency in C/C++ for test environments or stimulus generation.
• Experience implementing directed and constrained-random testbenches for communication PHYs, Ethernet, packet processing, PCIe, and multi-CPU environments.
• Knowledge of verification IP and functional coverage techniques.
• Experience with gate-level simulations of delay-annotated netlists.
• Exposure to FPGA emulation and lab validation.
• Strong communication skills and ability to provide technical leadership in a fast-paced environment.

Education Requirements

BS in Electrical Engineering or a related field plus 5 years of relevant experience, or MS plus 3 years of relevant experience, or Ph.D. (posting indicates these degree + experience combinations as the qualification guideline).

About the Company

Company: MaxLinear

Headquarters: Carlsbad, CA, United States

Fabless semiconductor company that designs RF, analog, digital, and mixed-signal system-on-chip solutions for access and connectivity, data center and optical interconnects, wired/wireless infrastructure, and industrial and multi-market applications.