Staff ASIC RTL Design Engineer

Job Title

Staff ASIC RTL Design Engineer

Role Summary

The Staff ASIC RTL Design Engineer will be part of the ASIC Digital Design team, responsible for designing and developing advanced semiconductor products. This role involves working closely with cross-functional teams to drive design innovation and efficiency in complex projects.

Experience Level

Mid-level, typically requiring several years of experience in ASIC design and RTL methodologies.

Responsibilities

The key responsibilities include:

• Designing and implementing RTL for complex ASIC projects.
• Collaborating with verification and implementation teams to ensure design integrity.
• Participating in design reviews and providing technical feedback.
• Debugging designs and resolving issues throughout the development process.
• Optimizing designs for performance, area, and power consumption.

Requirements

Must-have skills include:

• Strong experience in RTL design using Verilog or VHDL.
• Knowledge of ASIC design methodologies and tools.
• Experience with synthesis, place and route, and timing closure.
• Ability to work in a team-oriented environment.
• Excellent problem-solving and communication skills.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is typically required.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.