Staff ASIC Design Engineer
Design and implement RTL and micro-architecture for SoC blocks used in edge AI computer-vision products, with broad exposure across video compression, image processing, vector compute, processor cores, and memory subsystems.
The role participates across the full chip flow from architecture and RTL implementation to verification, synthesis optimization, and chip bring-up.
Senior-level. The posting specifies 5–10 years of relevant VLSI / ASIC design experience.
Primary technical responsibilities include:
Must-have technical skills and attributes:
Master's degree in Electrical, Electronics, or Computer Engineering is specified (Master’s degree required). The posting also specifies 5–10 years of relevant experience.
Company: Ambarella
Headquarters: Santa Clara, California, USA
Ambarella is a leader in computer vision and video processing technology, providing advanced solutions that enhance the performance of video applications. Focused on quality and innovation, Ambarella develops products for diverse uses, including autonomous vehicles, surveillance systems, and smart cameras, aiming to deliver pristine imagery and efficient compression while minimizing power consumption.
