Staff Applications Engineer, Synthesis and Formal Verification

Job Title

Staff Applications Engineer, Synthesis and Formal Verification

Role Summary

Customer-facing applications engineer responsible for technical engagements across RTL, synthesis, formal equivalence, and physical design from evaluation through tapeout. Work with semiconductor design teams to diagnose and resolve synthesis and equivalence issues and to scale robust RTL-to-netlist methodologies.

Experience Level

Senior - typically requires 5 or more years of hands-on ASIC/SoC design or EDA applications engineering experience, with at least one production design cycle or tapeout.

Responsibilities

Provide technical partnership to customer design teams and Synopsys product groups to enable successful synthesis and equivalence deployments.

• Own customer technical relationships for synthesis, equivalence checking, and RTL methodology from evaluation through tapeout.
• Debug complex synthesis and Formality issues, reproduce problems when possible, isolate root causes, and deliver recommendations or escalations with documented test cases.
• Advise on RTL-to-netlist methodology, including hierarchy, datapath optimization, physical-aware synthesis, clock gating, multi-bit registers, and handoff to place-and-route.
• Analyze synthesis results, timing reports, constraint files, library characterization, and PPA outcomes to identify optimization opportunities and improve correlation with implementation.
• Create and maintain reusable scripts, reference flows, application notes, debug guides, and training materials for global teams.
• Translate recurring customer issues into use cases and product feedback for R&D; validate fixes in real customer contexts.
• Support technical evaluations, benchmarks, and adoption of new synthesis and formal verification technologies.

Requirements

Key technical skills and practical experience required to perform the role.

• Must-have: 5+ years of hands-on ASIC or SoC design, logic synthesis, formal equivalence checking, or EDA applications engineering; at least one production design cycle or tapeout.
• Must-have: Strong working knowledge of Verilog or SystemVerilog RTL, logic synthesis fundamentals, timing constraints (SDC), standard-cell libraries, and RTL-to-netlist design flows.
• Must-have: Practical experience with formal equivalence checking: setting up comparisons, investigating setup issues, and analyzing proof failures or inconclusive results.
• Must-have: Proficiency with Tcl scripting and Linux command-line environments for automating flows and parsing reports.
• Nice-to-have: Direct experience with Synopsys Design Compiler, Fusion Compiler, RTL Architect, or Formality and familiarity with static timing analysis tools such as PrimeTime.
• Nice-to-have: Experience with UPF/low-power design, hierarchical SoCs, advanced process nodes, or physical-aware synthesis.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is preferred; the posting also accepts equivalent hands-on experience in ASIC design or EDA applications.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.