Staff Applications Engineer
SynopsysJob Title
Staff Applications Engineer
Role Summary
Provide formal verification expertise to customer design teams: deploy formal methodologies, diagnose tool and design issues, and help customers adopt formal techniques across SoC projects. The role is customer-facing within Synopsys' engineering organization and works closely with R&D and product engineering to improve verification flows and tool performance.
Experience Level
Senior-level. Typically requires 5–7 years of hands-on RTL design or verification experience deploying advanced verification methodologies.
Responsibilities
Primary responsibilities include leading formal verification engagements, troubleshooting formal runs, and transferring best practices to customers and internal teams.
- Lead formal verification deployments and assess verification gaps and RTL complexity to recommend practical methodologies.
- Diagnose root causes of formal tool performance issues (state-space explosion, over-constrained environments, poorly scoped properties) and optimize testbenches and abstraction strategies.
- Identify candidate blocks and scenarios for property checking, sequential equivalence checking, connectivity checks, and formal coverage analysis.
- Develop and deliver technical training and practical guidance on formal features and product updates.
- Collaborate with Synopsys R&D and product engineering to communicate customer priorities and feature requests.
- Support customers during complex formal runs, including data-path logic verification, math function checks, and assertion-based integration.
- Build reusable formal verification flows and best practices for reuse across engagements.
Requirements
Technical and professional requirements. See Education Requirements below for formal degree expectations.
- 5–7 years of hands-on experience in RTL design or verification and deploying verification methodologies in production environments.
- Deep understanding of formal verification techniques: formal property checking, sequential equivalence checking, formal coverage analysis, and connectivity checking.
- Ability to read and reason about micro-architecture and RTL implementations; strong working knowledge of Verilog or VHDL.
- Proficiency in Unix/Linux environments and scripting for automation (Tcl, Perl, Python, bash/csh).
- Nice-to-have: Hands-on experience with assertion-based verification and prior use of formal verification tools.
- Nice-to-have: Experience in verification consulting or managing verification responsibility for complex hardware designs.
- Strong written and verbal communication skills and the ability to work autonomously with customers.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering or Computer Engineering from an accredited institution.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
