Staff Application Engineer, Physical Design

Job Title

Staff Application Engineer, Physical Design

Role Summary

Provide hands-on support to customers for physical implementation and design closure using Synopsys tools, focusing on Fusion Compiler and advanced-node flows. Work with customers and internal R&D to debug implementation issues, improve workflows, and drive tapeout readiness.

Experience Level

Senior - at least 5 years of hands-on ASIC, physical design, implementation, or CAD engineering experience; experience working with customers and tapeout schedules.

Responsibilities

Primary responsibilities include customer support, technical debugging, and automation to enable successful tapeouts.

• Support customers through RTL-to-GDS implementation, signoff, and tapeout readiness.
• Debug complex issues in timing, power, congestion, routing, and runtime at advanced nodes (5nm/3nm and below).
• Provide practical guidance on synthesis, place-and-route, timing closure, and power optimization.
• Build and maintain automation scripts (TCL, Python) to streamline workflows and reduce turnaround time.
• Use AI-assisted tools and automation to accelerate debugging and improve productivity.
• Collaborate with internal R&D to reproduce customer issues and feed real-world cases into product development.
• Present technical recommendations to senior customer engineers and design leads during critical project phases.
• Work across the full RTL-to-GDS flow from implementation through signoff.

Requirements

Key must-have skills and relevant nice-to-have qualifications.

• Must-have: 5+ years hands-on ASIC/physical design, implementation, or CAD engineering experience (customer-facing experience preferred).
• Must-have: Direct experience with RTL-to-GDS implementation flows: synthesis, place-and-route, timing closure, and physical design optimization.
• Must-have: Strong practical knowledge of Fusion Compiler, ICC2, or equivalent digital implementation tools.
• Must-have: Proficiency scripting in TCL and Python to automate tasks and workflows.
• Must-have: Solid understanding of timing, power, congestion, routing, and design-closure methodologies.
• Must-have: Business-level English and ability to communicate technical issues clearly to senior engineers and managers; willingness to engage with customers onsite and remotely.
• Nice-to-have: Working knowledge of Formality, PrimeTime, or related EDA signoff tools.
• Nice-to-have: Experience with advanced process nodes (7nm and below), and hands-on experience resolving closure challenges at 5nm/3nm.
• Nice-to-have: Demonstrated experience leveraging AI-assisted workflows to improve engineering productivity.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field is required (as stated). No other degrees or certifications were specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.