Staff Application Engineer – ECO Timing

Job Title

Staff Application Engineer – ECO Timing

Role Summary

Provide hands-on technical support to customer teams on timing signoff, extraction, and ECO flows for advanced-node ASIC projects. Act as the field technical expert interfacing between customers, Synopsys R&D, and sales to resolve design-closure issues and influence product direction.

Work with the ECO Field team in Hyderabad to deliver technical guidance, training, automation, and validation that help customers achieve tapeout and PPA targets on advanced process nodes.

Experience Level

Senior - staff-level role. Target experience: approximately 6–8 years in semiconductor design, place & route, STA, extraction, and ECO flows.

Responsibilities

The role combines customer-facing problem solving, technical enablement, and collaboration with product teams. Key responsibilities include:

• Diagnose and resolve complex timing, extraction, and design-closure issues on live silicon projects using Synopsys STA, ECO, and P&R tools.
• Collaborate with R&D to validate features, reproduce customer issues, and translate customer needs into product requirements.
• Deploy and promote best practices for timing signoff, parasitic annotation, and physical design methodologies for advanced nodes.
• Deliver technical training, demos, and knowledge transfer to customer engineering teams and field staff.
• Support projects from early design through tapeout, including constraint setup and multi-die timing challenges.
• Partner with Sales and technical managers to scope solutions and communicate technical tradeoffs to engineering and management stakeholders.
• Develop automation and scripts (TCL, Perl, etc.) to streamline workflows and shorten turnaround on critical tasks.

Requirements

Must-have technical skills and experience; nice-to-have items noted.

• Must-have: 6–8 years of hands-on semiconductor design experience with direct involvement in Place & Route, Static Timing Analysis, extraction, and ECO flows.
• Must-have: Deep knowledge of timing and physical constraint methodologies, parasitic annotation, and timing analysis for complex ICs.
• Must-have: Proven execution on silicon projects through physical design and timing closure, especially on advanced nodes (7nm, 5nm, 3nm).
• Must-have: Strong scripting ability in TCL and Perl to automate design tasks and build custom flows.
• Must-have: Solid understanding of ASIC design flow, VLSI fundamentals, and CAD engineering across the full design cycle.
• Nice-to-have: Prior customer-facing experience in applications, field engineering, or technical support.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or equivalent technical discipline - or equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.