Staff Analog Mixed-Signal Layout and Methodology Engineer

Job Title

Staff Analog Mixed-Signal Layout and Methodology Engineer

Role Summary

Design and optimize analog and mixed-signal IC layouts from concept through sign-off, focusing on device matching, EMIR/ESD awareness, parasitic minimization, and first-pass verification success. The role partners with circuit designers, verification teams, and global layout teams to produce reliable, manufacturable layouts and to develop repeatable methodology and automation.

Experience Level

Senior-level. The posting requests approximately 5+ years of relevant analog/mixed-signal layout experience.

Responsibilities

Primary responsibilities include hands-on layout, verification, methodology development, and cross-team coordination.

• Create and optimize analog/mixed-signal layouts with attention to device matching, EMIR, and parasitic reduction using Custom Compiler SDL or Virtuoso XL.
• Own top-down macro floorplanning and drive layout from architecture to final sign-off, coordinating with circuit designers and verification teams.
• Run and resolve DRC, LVS, Antenna, DFM, and other physical verification checks to minimize rework.
• Perform PERC verification for ESD and latch-up and proactively mitigate risks before tape-out.
• Use internal AI and automation tools to increase layout productivity and reduce manual effort.
• Collaborate with global layout teams to share best practices and align methodologies.
• Document methodologies and improvements so processes are repeatable and scalable.
• Work with automation engineers to script and automate layout and verification flows.

Requirements

Required technical skills and demonstrated experience; listed as must-have and nice-to-have.

• Must-have:
  • Proven expertise in analog/mixed-signal layout including device and signal matching, EMIR awareness, and parasitic optimization.
  • Hands-on experience with custom layout tools such as Custom Compiler SDL or Virtuoso XL.
  • Strong knowledge of DRC, LVS, Antenna, DFM, and other physical verification processes.
  • Experience with PERC verification for ESD and latch-up and the ability to remediate issues.
  • Ability to own floorplanning and drive layout from high-level architecture to sign-off.
  • Proven collaboration skills with distributed teams and ability to document and share methods.
• Nice-to-have:
  • Scripting skills (TCL, Perl, Python) to automate tasks and improve flows.
  • Experience preparing clear methodology documentation (MS Word, PowerPoint).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related technical field. The posting specifies approximately 5+ years of relevant experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.