Staff Analog Layout Engineer

Job Title

Staff Analog Layout Engineer

Role Summary

As a Staff Analog Layout Engineer in Central Engineering, you will design and deliver complex analog and mixed-signal physical layouts for advanced process nodes. You will work with circuit designers, lead analog macro layout efforts, and ensure designs meet performance, reliability, and schedule targets.

Experience Level

Senior-level. 6–10 years of hands-on analog and custom layout experience.

Responsibilities

Deliverable-focused responsibilities include:

• Independently create complex analog and mixed-signal layouts across advanced nodes (deep sub-micron, FinFET, GAA) using industry-standard EDA tools.
• Translate schematics into optimized physical layouts, collaborating with circuit designers to preserve intent and performance.
• Drive physical verification closure and resolve DRC, LVS, ERC, and antenna issues within project timelines.
• Perform EM/IR analysis and implement layout solutions to address electromigration and IR drop.
• Apply advanced layout techniques: device matching, symmetry, shielding, clock routing, and parasitic (RC) minimization.
• Lead analog macro layout development, owning quality, schedule, and alignment with project goals.
• Mentor and support junior engineers through design reviews and best-practice guidance.

Requirements

Key technical skills and experience required. Education requirements are summarized separately below.

• Must have: 6–10 years of hands-on high-speed analog and custom layout design experience.
• Must have: Proficiency with EDA/CAD tools (e.g., Cadence Virtuoso, Mentor Graphics) for schematic-to-layout and physical design execution.
• Must have: Experience with physical verification flows and resolving DRC, LVS, ERC, and antenna violations.
• Must have: Practical experience in EM/IR analysis, biasing strategies, and robust power/ground routing methodologies.
• Must have: Expertise in advanced layout techniques including device matching, symmetry, signal flow optimization, and parasitic reduction.
• Nice to have: Proven delivery across multiple technology nodes and experience with reliability measures such as ESD and latch-up prevention.

Education Requirements

Bachelor's or master's degree (BE/B.Tech or MS/M.Tech) in Electronics & Communication, Electrical & Electronics Engineering, or a related field from a reputed institution.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.