Staff Analog Design Engineer, TX/RX Datapath

Job Title

Staff Analog Design Engineer, TX/RX Datapath

Role Summary

Hands-on transistor-level analog design lead responsible for the transmit and receive datapath of a high-speed SerDes on an IO chiplet. You will carry blocks from specification through silicon characterization and work closely with layout, package/signal-integrity, backend, and firmware engineers.

Work spans porting proven datapath blocks to new process nodes and designing new blocks for next-generation links, with direct involvement in verification, layout co-design, and silicon bring-up.

Experience Level

Senior — requires 8+ years of hands-on analog and mixed-signal circuit design experience.

Responsibilities

Primary technical responsibilities and deliverables for the SerDes datapath.

• Own transistor-level design of the SerDes transmit path: output drivers (SST/CML), pre-drivers, serializers, and transmit-side FFE.
• Own transistor-level design of the receive front-end: input termination/ESD-aware networks, CTLE, VGA, samplers, and ADC-based front-ends where applicable.
• Design and verify equalization (DFE/FFE): architecture, tap resolution, adaptation behavior, and trade studies.
• Derive and defend block-level specifications from link budgets covering insertion loss, crosstalk, reflection, jitter, and BER targets.
• Build verification environments: testbenches, PVT corner coverage, six-sigma Monte Carlo, transient noise, post-layout back-annotated simulation, and provide behavioral/Verilog-A models for full-chip verification.
• Perform link and channel modeling (MATLAB, Python or equivalent): S-parameter channel and package models, statistical eye and BER analysis.
• Drive layout collaboration on floorplan, matching, shielding, current density, and parasitic control; co-design with package/SI on bump maps and escape routing.
• Support testboard design, silicon bring-up, and bench characterization; correlate measured performance with simulation.

Requirements

Core technical qualifications and preferred additional skills.

Must-have

• 8+ years of hands-on analog and mixed-signal circuit design experience.
• Demonstrated ownership of a SerDes transmit or receive datapath block through to working silicon.
• Deep knowledge of high-speed driver design, receive front-end design, equalization, and interfacing clocking/CDR blocks.
• Practical command of jitter and noise analysis: decomposition, budgeting, and simulation methodologies.
• Circuit design experience in advanced FinFET or GAA process nodes and use of industry-standard analog design/simulation tools (e.g., Cadence Virtuoso, Spectre, Monte Carlo, post-layout simulation).
• Link/channel modeling experience (MATLAB, Python, S-parameter models) and silicon bring-up/bench debug using scopes and BERTs.

Nice-to-have

• Die-to-die interconnect experience (UCIe, BoW, or proprietary D2D PHY) and short-reach, low-energy-per-bit constraints.
• PAM4 signaling and DSP-based receiver architectures, including ADC-based front-ends.
• Familiarity with UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7 specifications.
• Experience porting datapath blocks across process nodes and realistic cost assessment of that effort.
• IBIS-AMI model generation, SerDes ATE, and production test development.
• Participation in or contribution to standards bodies.

Education Requirements

Posting specifies BS, MS, or PhD in Electrical Engineering. The role also specifies 8+ years of hands-on analog and mixed-signal circuit design experience.

About the Company

Company: d-Matrix

Headquarters: Santa Clara, California, United States

d-Matrix is a Santa Clara–based startup developing highly programmable in-memory computing architectures and accompanying software to accelerate generative AI and other AI workloads, focusing on hardware-software co-design for cloud and edge applications.