Staff Analog Design Engineer

Job Title

Staff Analog Design Engineer

Role Summary

Lead analog-mixed-signal IC design for next-generation AI inference accelerators, owning circuits for the in-memory-compute engine and the die-to-die serial interface. Drive designs from schematic through silicon bring-up and collaborate with layout, backend, and integration teams to deliver silicon-ready subsystems in deep sub-micron process nodes (7nm and below).

Experience Level

Senior-level (Staff). Guidance: 5+ years of professional experience in high-speed analog/mixed-signal circuit design.

Responsibilities

Primary responsibilities include circuit design, verification, integration, and silicon bring-up for analog subsystems.

• Design analog-mixed-signal circuits using Cadence, Synopsys, and industry-standard tools.
• Develop schematic-level circuits and perform system-level performance analysis.
• Build testbenches for simulation and verification, including Monte Carlo and PVT analysis.
• Guide layout engineers on circuit layout in deep sub-micron nodes and perform minor hands-on layout adjustments as needed.
• Provide extracted circuit models and partner with backend/digital teams for integration and verification.
• Support testboard design, silicon bring-up, bench debug, and device characterization.
• Develop scripts and infrastructure to support silicon bring-up and automated test validation.

Requirements

Must-have technical skills and experience.

• 5+ years of professional experience in high-speed circuit design (examples: phase interpolators, clocking, PLLs).
• Experience with schematic capture, SPICE simulation, and Monte Carlo yield analysis.
• Experience with circuit layout, extraction, and back-annotated simulation workflows.
• Experience with channel modeling using MATLAB or similar tools.
• Strong cross-functional communication and collaboration skills across distributed teams.
• Strong analytical and problem-solving skills; ability to manage multiple priorities in a fast-paced environment.

Nice-to-have / preferred:

• SerDes verification & characterization, analog verification infrastructure, or reliability analysis (EM, IR drop, ESD/latch-up).
• Experience owning low-jitter PLLs, phase interpolators, or CDR loops through silicon at 25 Gbps+ per lane.
• TX/RX datapath design experience (CTLE, VGA, samplers, DFE/FFE, PAM4/DSP-based receivers).
• Die-to-die interconnect experience (UCIe, BoW, D2D PHY) or familiarity with OIF CEI, IEEE 802.3, PCIe Gen6/7 specs.

Education Requirements

BS, MS, or PhD in Electrical Engineering.

About the Company

Company: d-Matrix

Headquarters: Santa Clara, California, United States

d-Matrix is a Santa Clara–based startup developing highly programmable in-memory computing architectures and accompanying software to accelerate generative AI and other AI workloads, focusing on hardware-software co-design for cloud and edge applications.