Staff Analog and Mixed-Signal Design Engineer

Job Title

Staff Analog and Mixed-Signal Design Engineer

Role Summary

Design and deliver transistor-level analog and mixed-signal circuits for high-speed SerDes IP used in datacenter, automotive, and communications applications. Work within the Silicon IP R&D team, collaborating with digital RTL engineers, layout specialists, and characterization teams to produce silicon-proven IP.

Focus on circuit design, verification, and layout verification to meet performance, power, and area targets at advanced FinFET process nodes.

Experience Level

Senior (staff level). Guidance: multiple years of hands-on analog/mixed-signal design experience; candidates should have at least several years of relevant experience.

Responsibilities

Primary responsibilities include transistor-level design, verification, layout interaction, and mentoring.

• Develop sub-block specifications from SerDes standards (PCIe, Ethernet, CPRI) for analog circuits targeting 112Gbps and above.
• Design and optimize transistor-level circuits (e.g., receive equalizers, drivers, serializers/deserializers, VCOs, PLLs/DLLs, ADCs/DACs, bandgaps) in advanced FinFET nodes.
• Create and execute verification strategies using SPICE-class simulators to validate power, area, and performance across PVT corners.
• Oversee and collaborate with layout engineers to minimize parasitics, manage device mismatch, and mitigate proximity- and stress-induced effects.
• Work directly with digital RTL teams to define interfaces, calibration, and control algorithms that integrate with analog circuits.
• Present simulation results, corner analysis, and design tradeoffs in peer reviews and technical customer discussions.
• Mentor junior engineers on design fundamentals, layout best practices, and verification methodology; review their work and provide guidance.

Requirements

Must-have technical skills and experience required to perform the role.

• Silicon-proven track record implementing TX, RX, and clock-path circuits within SerDes IP that have taped out and been validated in production.
• Hands-on experience designing multiple circuit types from the list: receive equalizers, data samplers, voltage/current-mode drivers, serializers/deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, DACs.
• Proven ability to optimize FinFET CMOS layout to minimize parasitics and manage local device mismatch.
• Proficiency with HSpice, FineSim, PrimeSim, or similar SPICE simulators, and experience with EDA tools for schematic entry, layout, and design verification.
• Working knowledge of ESD techniques, layout practices, and design-for-reliability issues (electromigration, IR drop, aging).
• Experience with scripting and automation (Python, TCL, Perl, C, or MATLAB).
• Ability to debug silicon issues and reduce design risk through corner analysis and thorough verification.

Nice-to-have:

• Familiarity with digital timing analysis tools such as PrimeTime or NanoTime.
• Experience with calibration/adaptive algorithms and close collaboration with digital teams.

Education Requirements

MASc or PhD with 3+ years of CMOS analog and mixed-signal circuit design experience, or Bachelor's degree with additional equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.