Staff Analog and Mixed-Signal Design Engineer

Job Title

Staff Analog and Mixed-Signal Design Engineer

Role Summary

Senior analog/mixed-signal design engineer responsible for transistor-level design, verification, and silicon bring-up of high-speed SerDes and related analog IP. The role sits on the Silicon IP R&D team working with digital RTL engineers, layout specialists, and characterization teams to deliver production-quality IP for datacenter, automotive, and communications applications.

Experience Level

Senior. The posting indicates experienced candidates; degree-based guidance specifies 3+ years of CMOS analog and mixed-signal design experience for advanced degrees or equivalent experience for other degrees.

Responsibilities

Primary responsibilities include design, verification, layout coordination, and mentoring; examples follow.

• Define analog sub-block specifications from SerDes standards (PCIe, Ethernet, CPRI) for 112Gbps, 128Gbps, 224Gbps and higher.
• Design and optimize transistor-level circuits: RX/TX chains, serializers/deserializers, VCOs, PLLs/DLLs, phase interpolators, bandgaps, ADCs/DACs.
• Develop and execute verification strategies using Hspice/Finesim/PrimeSim or equivalent across PVT corners to validate power, area, and performance.
• Oversee and review layout to minimize parasitics, manage device mismatch, and mitigate proximity and stress-induced variation.
• Collaborate with digital RTL teams to define interfaces, calibration, and adaptation algorithms for mixed-signal control loops.
• Present simulation results, corner analysis, and design tradeoffs in peer reviews and customer-facing technical discussions.
• Mentor junior engineers on circuit design, layout best practices, and verification methodology; review their deliverables.

Requirements

Must-have technical skills and experience; degree information is summarized separately under Education Requirements.

• Silicon-proven track record implementing TX, RX, and clock-path circuits within SerDes with taped-out and production-validated designs.
• Hands-on experience designing multiple block types listed above (equalizers, samplers, drivers, serializers/deserializers, VCOs, PLLs/DLLs, ADCs/DACs).
• Proven ability to optimize FinFET CMOS layout to minimize parasitic R/C while managing local device mismatch and proximity effects.
• Proficiency with SPICE simulators (Hspice, Finesim, PrimeSim or equivalent) and EDA tools for schematic entry, layout, and design verification.
• Working knowledge of ESD techniques and design-for-reliability concerns (electromigration, IR drop, aging).
• Scripting and automation experience (Python, TCL, Perl, C, or MATLAB).
• Nice-to-have: experience with digital timing analysis tools such as PrimeTime or Nanotime.

Education Requirements

MASc or PhD with 3+ years of CMOS analog and mixed-signal circuit design experience, or a Bachelor's degree with additional equivalent practical experience. Relevant background in CMOS analog/mixed-signal design and SerDes is expected.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.