STA Engineer

Job Title

STA Engineer

Role Summary

Work on static timing analysis (STA) and synthesis for high-performance, low-power Wi‑Fi SoCs and subsystems. The role leads timing-closure activities across pre-layout and post-layout phases and collaborates with architecture, RTL, verification, DFT, and physical design teams to deliver silicon on aggressive schedules.

Experience Level

Mid-level — guidance from the posting: 6–8 years of ASIC/SoC STA and synthesis experience.

Responsibilities

Primary responsibilities focus on timing closure, synthesis quality, and automation/methodology development.

• Drive subsystem- and full-chip STA for pre-layout and post-layout stages; support signoff activities.
• Perform timing analysis with PrimeTime (or equivalent) and identify/debug timing violations; recommend micro-architectural or implementation changes.
• Develop and validate SDC constraints, including multi-mode multi-corner (MMMC) setups; manage I/O timing budgets.
• Provide actionable timing feedback at block, subsystem and full-chip levels; define ECO guidance and root-cause analysis.
• Manage large-scale MMMC STA runs via automation, partitioning, and efficient resource allocation.
• Perform synthesis (including low-power flows), validate QoR, and ensure clean handoff to physical design; execute logical equivalence checking (LEC).
• Implement functional ECOs (including conformal ECOs) and low-power checks; balance power, performance, and area (PPA) tradeoffs.
• Develop and maintain automation and methodology scripts (TCL, Perl, Python) and AI-driven flows to improve STA and synthesis efficiency.

Requirements

Must-have technical skills and practical experience to perform independently on complex SoC timing and synthesis tasks.

• 6–8 years of hands-on ASIC/SoC STA and synthesis experience (including low-power synthesis and functional ECOs).
• Deep knowledge of STA and timing-constraint methodology; experience with MMMC timing closure, OCV/AOCV/POCV and signoff criteria.
• Experience with synthesis flows and logical equivalence checking (RTL-to-netlist and netlist-to-netlist).
• Understanding of SoC clocking and reset methodology and implementation; experience with multi-voltage designs and UPF-related checks.
• Scripting proficiency in TCL and Perl; experience using Python is preferred for automation.
• Hands-on experience with Synopsys PrimeTime and Synopsys Design Compiler or Cadence Genus.
• Ability to debug timing, recommend implementation fixes, and work cross-functionally with RTL, synthesis, and physical design teams.

Nice-to-have:

• Experience implementing ECOs with Conformal ECO tool and exposure to PrimePower (PTPX) for power estimation.
• Familiarity with wireless SoC domains (Wi‑Fi, Bluetooth), bus protocols (AXI/AHB), CDC issues, peripheral interfaces (PCIe, USB), and physical-design flows.

Education Requirements

Minimum qualifications include one of the following: Bachelor's degree in Science, Engineering, or a related field with 4+ years of relevant ASIC experience; OR Master's degree in Science, Engineering, or a related field with 3+ years of relevant experience; OR PhD in Science, Engineering, or a related field with 2+ years of relevant experience. Equivalent practical work experience is accepted in lieu of degree-based experience where stated.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.