STA Engineer - CPU Team

Job Title

STA Engineer - CPU Team (Senior Silicon Design Engineer)

Role Summary

Responsible for static timing analysis, margining, and yield-focused timing optimization of high-frequency CPU/APU cores. Work within the AMD Cores team and coordinate with RTL, physical design, verification, characterization, and yield engineering to achieve timing closure from RTL freeze through tapeout.

Experience Level

Senior. The posting lists a minimum of 2+ years of STA experience on high-performance digital or CPU/GPU/high-frequency ASIC designs.

Responsibilities

Primary responsibilities include timing signoff, margining, variability and yield analysis, and coordinating timing fixes with physical design.

• Lead static timing analysis and timing closure for high-frequency CPU/APU cores (4+ GHz target frequencies).
• Perform timing signoff across PVT corners and voltage/temperature combinations; resolve setup, hold, and transition violations.
• Develop and maintain timing constraints (SDC) for complex multi-mode, multi-corner clocking architectures.
• Analyze and optimize critical paths to meet frequency targets while controlling power impact.
• Execute timing ECOs and coordinate implementation with physical design teams (place & route).
• Define and implement timing margins for process variation, voltage droop, aging, temperature gradients, and OCV.
• Perform statistical timing analysis (SSTA), AOCV/POCV/SOCV analysis, Monte Carlo simulations, PBA/GBA, and other variability-aware analyses to improve timing yield.
• Develop IR-drop/voltage-aware timing methodologies and evaluate aging effects (NBTI, HCI, EM) and derating factors.
• Collaborate with yield engineering to identify timing sensitivities and support binning strategies based on frequency/voltage guardbands.

Requirements

Concise list of required and preferred skills. Education requirements are listed separately below.

• Must-have:
  • 2+ years of hands-on STA experience for high-performance digital designs.
  • Experience on CPU, GPU, or other high-frequency ASIC designs and leading timing closure for complex SoCs through tapeout.
  • Proven ability to perform timing signoff across multiple PVT corners and validate setup/hold/transition constraints.
  • Experience with SDC constraint development, timing ECO flow, and critical-path optimization.
  • Knowledge of statistical timing (SSTA), AOCV/POCV/SOCV methodologies, and voltage-aware timing techniques.
• Nice-to-have:
  • Exposure to physical design flows (synthesis, placement, routing, floorplanning) and CTS recipe definition.
  • Familiarity with Synopsys and Cadence toolchains (e.g., PrimeTime, Fusion Compiler, Innovus/Genus, Design Compiler, IC Compiler II).
  • Experience with timing correlation, standard cell characterization, FinFET/GAA timing characteristics, 3D IC or chiplet timing analysis, or ML applications for timing prediction.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.