STA Engineer

Job Title

STA Engineer

Role Summary

Owner of static timing analysis (STA) and synthesis for low-power Wi‑Fi SoCs and subsystems. Responsible for timing closure from block/HM to full-chip, synthesis quality, and low‑power implementation while collaborating with architecture, RTL, verification, DFT, and physical design teams.

Experience Level

Mid-level — typically 6–8 years of ASIC/SoC STA and synthesis experience.

Responsibilities

Deliver timing closure, synthesis quality, and automation across pre- and post-layout implementation for complex SoCs.

• Perform subsystem and full‑chip STA (pre-layout and post-layout) and drive timing closure and signoff using PrimeTime or equivalent.
• Develop and validate SDC constraints, including multi-mode multi-corner (MMMC) setups and I/O timing budgets.
• Identify timing bottlenecks, perform root-cause analysis, and propose micro-architectural or implementation ECOs.
• Perform synthesis (including low-power synthesis), validate QoR, run LEC, and ensure clean handoff to physical design.
• Implement functional ECOs (including Conformal ECOs) and manage netlist-level fixes.
• Manage large-scale MMMC STA runs with automation, partitioning, and efficient resource usage.
• Balance power, performance, area (PPA) constraints and perform low-power verification and checks (UPF, multi-voltage flows).
• Develop and maintain automation and methodology scripts (TCL, Perl, Python) and AI-driven flows for STA and synthesis tasks.

Requirements

Must-have skills and technologies for immediate contribution.

• 6–8 years experience in ASIC/SoC STA and synthesis (including low-power implementation).
• Strong knowledge of STA methodology, timing constraints, and timing closure processes (MMMC, OCV/AOCV/POCV).
• Experience with timing signoff requirements and full-chip timing closure.
• Experience with synthesis tools and LEC (RTL-to-netlist and netlist-to-netlist).
• Practical understanding of SoC clocking and reset methodology.
• Scripting proficiency in TCL and Perl; Python experience preferred.
• Hands‑on experience with Synopsys PrimeTime and Synopsys Design Compiler or Cadence Genus.
• Experience with ECO flows and low‑power design techniques (multi‑voltage, UPF).

Nice-to-have:

• Experience with Conformal ECO, PrimePower (PTPX), physical design flows, CDC and bus protocols (AXI/AHB), and wireless SoC experience (Wi‑Fi/Bluetooth).

Education Requirements

Bachelor's degree in Science, Engineering, or a related field plus 4+ years of ASIC/SoC design experience; OR Master's degree plus 3+ years; OR PhD plus 2+ years. Equivalent practical experience in ASIC/SoC design is acceptable.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.