STA Design Engineer - Static Timing Analysis

Job Title

STA Design Engineer — Static Timing Analysis

Role Summary

Perform static timing analysis and timing closure for complex cores and full-chip SoCs to ensure performance, power and timing signoff. Work within the STA team to validate timing models, produce timing ECOs, and provide actionable feedback to RTL, synthesis and physical design teams.

Collaborate with cross-functional teams to improve timing methodologies, automate timing and power data processing, and support production projects to achieve timing signoff milestones.

Experience Level

Mid-level (typical experience: 3–7 years). The posting indicates candidates with several years of relevant ASIC/STA experience, commonly 4+ years.

Responsibilities

Core responsibilities include STA signoff, methodology development, and project delivery:

• Perform static timing analysis and timing closure for complex cores and full-chip SOCs.
• Analyze gate-level PNR netlists and produce timing ECOs to resolve violations.
• Develop and refine timing constraints and signoff checklists; ensure compliance with signoff criteria.
• Provide timing-related feedback to RTL, synthesis and physical design teams to improve PPA.
• Improve STA accuracy and flows to reduce turnaround time; enhance static/dynamic timing methodologies.
• Automate timing and power data mining, processing and reporting.
• Contribute to project proposals, define milestones and deliverables, and provide production support.
• Troubleshoot and resolve timing issues across development phases to meet project goals.

Requirements

Key technical skills and competencies. Education and degree/year requirements are in the Education Requirements section below.

• Expertise with STA tools such as Synopsys PrimeTime, PrimeShield or Siemens/Ansys Tempus for hierarchical analysis in large SoCs.
• Hands-on experience with timing-closure utilities: Tweaker, PrimeClosure, PTECO, Tempus ECO or equivalent.
• Strong scripting and automation skills (Python, TCL, Perl) to develop flows and data-processing tools.
• Solid knowledge of ASIC design flows (RTL-to-GDS) and timing signoff practices.
• Experience working with gate-level PNR netlists and signoff-quality timing models.
• Good problem-solving skills, attention to detail, and ability to work in a fast-paced, multidisciplinary engineering environment.
• Good communication and teamwork skills for cross-functional collaboration and production support.
• Nice-to-have: familiarity with Design for Parametric Yield, extraction and circuit simulation tools/environments.

Education Requirements

Minimum qualifications specify one of the following: Bachelor's degree in Science, Engineering or related field plus 4+ years of relevant ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering or related field plus 3+ years experience; OR PhD in Science, Engineering or related field plus 2+ years experience. The posting also allows equivalent practical experience in lieu of the listed degree/year combinations.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.