Sr. Verification Engineer (ASIC)

Job Title

Sr. Verification Engineer (ASIC)

Role Summary

Senior verification engineer for an ASIC program supporting a high-throughput modem and DSP‑intensive digital beamformer. Work spans IP, subsystem, and full SoC verification and includes CPU subsystems, interconnects, security, high-speed peripherals, modem datapath/PHY, DSP/beamforming compute, and mixed-signal interfaces.

You will help define verification strategy, methodology, and infrastructure, and own verification deliverables for assigned blocks or subsystems. The team treats constrained-random simulation, formal methods, and processor-driven testing as first-class tools and is building AI-assisted verification capabilities.

Experience Level

Senior - typically 5+ years professional ASIC/SoC functional verification experience (basic qualification specifies minimum five years). Candidates with equivalent experience and required skills will be considered.

Responsibilities

Lead verification planning, implementation, and sign-off for complex blocks and subsystems.

• Create verification strategies and measurable coverage goals from design specifications.
• Select and apply verification methods: constrained-random, formal analysis, directed/firmware-driven tests.
• Develop verification environments, reference models, scoreboards, protocol monitors, coverage components, and assertions.
• Drive functional coverage closure, regression health, and sign-off readiness across simulation and formal results.
• Build and maintain verification infrastructure, CI/regression systems, and reuse strategies across IP, subsystem, and SoC levels.
• Integrate and apply AI-assisted verification capabilities for stimulus generation, regression triage, and coverage analytics.
• Review testbench architecture and debug methodology; mentor junior engineers on verification methodology and debug practices.

Requirements

Must-have technical skills and experience.

• Minimum five years professional experience in ASIC or SoC functional verification.
• Hands-on expertise in SystemVerilog and UVM, or formal testbench development and maintenance.
• Experience with metric-driven verification: assertions and functional coverage planning and closure.
• Experience verifying complex digital control and datapath logic, including RTL and system-level debug.
• Experience developing verification infrastructure, regressions, and CI systems.
• Demonstrated ability to define verification strategy and translate specifications into test plans and coverage goals.

Nice-to-have (preferred):

• Background in wireless or space-based communications, modem/baseband, or DSP verification (LDPC, FEC, framing, beamforming).
• Formal verification on production silicon for connectivity, register maps, arbitration, CDC, or security properties.
• Interconnect/NoC verification experience (performance, bandwidth, QoS, deadlock analysis).
• Fault-tolerance and reliability verification (ECC, redundancy, fault injection).
• Experience developing C-based or portable stimulus for SoC, CPU boot, and firmware-driven scenarios.
• Experience applying AI/ML/LLM tooling to stimulus generation, regression triage, or coverage analysis.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field, or 7+ years equivalent practical experience.

About the Company

Company: IntelliPro Group

Headquarters: Irvine, California, United States

Global talent acquisition and HR solutions firm founded in 2009, providing recruitment, staffing, and workforce solutions across more than 160 countries. Focuses on connecting candidates with employment opportunities and offering inclusive hiring practices and HR services.