Sr. Timing Methodology Engineer

Job Title

Sr. Timing Methodology Engineer

Role Summary

Define, develop, and drive timing and power methodologies for AMD's Adaptive and Embedded Computing Group to enable silicon solutions with competitive power, performance and area (PPA) at advanced process nodes.

Work cross-functionally with architecture, product planning, process, design, and product engineering teams to resolve sign-off and modeling challenges for monolithic and 2.5/3DIC adaptive SoCs and FPGAs.

Experience Level

Senior. The posting specifies a senior role but does not list explicit years-of-experience guidance.

Responsibilities

Key responsibilities include developing and operationalizing timing and power sign-off methodologies and collaborating across teams to mitigate sign-off risk.

• Define, develop, optimize and drive design, timing, and power methodologies for advanced process nodes.
• Support sign-off and modeling methodologies at 2nm and beyond for monolithic and 2.5/3DIC adaptive SoCs and FPGAs.
• Collaborate with implementation and sign-off teams to ensure methodologies are adopted and effective.
• Work with CAD, power integrity, foundry teams and EDA vendors to quantify margins and develop mitigation strategies.
• Convert high-level requirements from product planning, foundry, and stakeholders into practical guidelines and flows for designers.
• Advocate technical solutions and enable design teams to meet PPA, schedule, and cost targets.

Requirements

Concise list of required and preferred qualifications.

• Must-have: Senior experience in timing/methodology and sign-off on advanced process nodes; strong background in physical design and sign-off flows and tools.
• Must-have: Proficiency with industry-standard physical design, analysis, and sign-off tools.
• Must-have: Programming/scripting skills (Python, Tcl, Perl).
• Must-have: Strong communication skills and proven ability to collaborate across architecture, product, CAD, foundry and implementation teams.
• Must-have: Experience with FPGA implementation tools and practical knowledge of FPGA implementation/sign-off flows.
• Required: Authorized to work in the United States; this role is not eligible for visa sponsorship.
• Nice-to-have: Experience with custom/physical design, power integrity, EDA vendor engagement, and 2.5/3DIC methodologies.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.