Sr Staff Test Architect Engineer

Job Title

Sr Staff Test Architect Engineer

Role Summary

Drive test strategy and development to maximize test coverage, product quality, and minimize test cost for analog/mixed-signal integrated circuits. Work as a technical lead interfacing with design, systems, and test engineering teams.

Contribute to development and deployment of DFT, ATE test programs, verification test benches, and simulation tools that accelerate test development, debug, and production checkout.

Experience Level

Senior-level. Target experience: approximately 5 to 12+ years in semiconductor test, validation, or related engineering roles.

Responsibilities

Core responsibilities for this role include:

• Define and drive test strategy to achieve required coverage, quality, and cost targets.
• Develop and implement DFT strategies and ATE test programs; deploy tests on production ATE platforms.
• Design, setup, and execute verification test benches and laboratory validation flows.
• Integrate ATE instruments and automated measurements into validation and production environments.
• Collaborate with design, systems, and test teams to debug failures and close verification gaps.
• Plan tasks and timelines, track progress, and present technical results to stakeholders.
• Collect, organize, and present technical data and test results to support product release decisions.

Requirements

Must-have technical skills and experience:

• Strong ATE programming skills and hands-on ATE test development experience.
• Design validation (DV) experience and ability to set up verification test benches.
• Strong understanding and practical use of ATE instruments and test equipment.
• Experience with Cadence Spectre / SimVision and AMS simulation flows.
• Working knowledge of Unix/Linux environments and scripting.
• SPICE simulation experience.
• HDL experience, including SystemVerilog.
• Functional understanding of instrument fundamentals, including control loops.
• Familiarity with oscilloscope, DMM, spectrum analyzer, and built-in debug tools.
• Design-for-Test (DFT) knowledge and experience implementing tests on ATE.
• Strong planning, organization, and technical communication skills.

Nice-to-have:

• Experience developing simulation tools that interface ATE environments with IC design and verification flows.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) or greater, or professional/industry equivalent experience.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.