Sr. Staff / Principal Physical Design Engineer

Job Title

Sr. Staff / Principal Physical Design Engineer

Role Summary

Lead physical implementation for advanced-node SoC designs from RTL to GDS, focusing on synthesis, placement, CTS, routing, extraction, verification, and signoff. Collaborate with front-end, DFT, power, and analog teams to optimize power, performance, and area (PPA) and ensure silicon success.

Position is onsite in San Jose, CA (5 days/week). Limited motivating context: work on advanced memory-centric semiconductor designs at leading process nodes.

Experience Level

Senior-level. The posting requests 8+ years of hands-on ASIC physical design experience with tapeout success.

Responsibilities

Work hands-on and provide technical leadership across the full physical design flow for high-performance blocks or full-chip SoCs.

• Lead implementation from synthesis through GDS for advanced process nodes (examples: 7nm, 5nm, 3nm).
• Execute and optimize synthesis, placement, CTS, and routing using Synopsys ICC2/Fusion Compiler or Cadence Innovus.
• Drive timing closure and signoff with PrimeTime, including multi-corner/multi-mode analysis, SI, AOCV/POCV, and crosstalk.
• Perform RC extraction (StarRC/Quantus) and ensure correlation between extraction and STA.
• Own physical verification signoff with Calibre; resolve DRC, LVS, ERC, and antenna issues for FinFET layouts.
• Perform power integrity analysis (RedHawk/RedHawk-SC): static/dynamic IR drop and EM analysis; optimize power grid and decoupling.
• Develop and maintain physical design flows and automation; mentor junior engineers and coordinate tapeout schedules.

Requirements

Key technical requirements are listed below. Items are split into must-have and nice-to-have where possible.

Must-have:

• 8+ years of hands-on ASIC physical design experience with demonstrated tapeout success.
• Expert-level proficiency in synthesis, placement, CTS, and routing using Synopsys or Cadence P&R tools.
• Deep knowledge of static timing analysis and PrimeTime signoff (multi-corner/multi-mode closure).
• Experience with physical verification flow and Calibre (DRC, LVS, ERC) and RC extraction correlation.
• Experience in IR drop and EM analysis using RedHawk or equivalent tools.
• Strong scripting or automation experience for flows and data analysis (Tcl/Perl/Python).

Nice-to-have:

• Experience at 5nm or 3nm process nodes and FinFET design rules.
• Familiarity with low-power techniques (UPF, clock gating, multi-Vt, voltage islands).
• Experience with ECO implementation, clock reconstruction, and useful-skew methodologies.
• Leadership or mentoring experience on complex SoC projects.
• Exposure to memory-centric systems (SSD SoC, HBM, HBF) or chiplet/D2D interconnects (UCIe) is a plus.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is required; Master's degree is preferred. (No alternate "equivalent experience" language was specified.)

About the Company

Company: SK hynix America

Headquarters: Icheon, South Korea

U.S. subsidiary of SK hynix, a global semiconductor company specializing in DRAM and NAND flash memory and related memory solutions for mobile devices, data centers, and consumer electronics. Focuses on advanced memory technologies, AI applications, and high-performance storage.