Sr. Staff Power Performance Architect
d-MatrixJob Title
Sr. Staff Power Performance Architect
Role Summary
Own pre-silicon power estimation for next-generation AI accelerators, build architectural power-estimation tools, and drive power-performance analysis into microarchitecture and silicon design. Work closely with front-end architects, DV engineers, and backend design teams and participate in RTL design, verification, and silicon bring-up.
Experience Level
Senior — 8+ years of relevant experience in IC power/performance architecture, RTL, or physical design.
Responsibilities
Primary responsibilities include pre-silicon power estimation, tool development, collaboration across teams, verification, and silicon validation.
- Own pre-silicon power estimation for design blocks at both RTL and physical-design levels.
- Develop an architectural power-estimation tool that models power from system configuration and die-level metrics for AI workloads.
- Partner with front-end architects, DV engineers, and backend design to identify power activity windows and define performance-monitoring requirements.
- Translate power and performance analysis into hardware capability improvements and die-level design changes.
- Lead micro-architecture and RTL design, synthesis, and logic/physical power-performance verification using industry CAD tools and advanced process technologies.
- Design and implement performance-enabling and power-saving monitoring functions; participate in silicon bring-up and validation.
Requirements
Must-have technical skills and experience.
- 8+ years of experience in IC power/performance architecture, RTL engineering, or physical design.
- Solid understanding of power, performance, micro-architecture, RTL, and physical design across the full IC design flow (architecture → uarch → RTL → schematic → layout → verification → fabrication → HVM).
- Familiarity with at least one EDA tool for power estimation.
- Practical experience spanning RTL, physical design, and automation; ability to build scripting utilities to improve team productivity.
- Programming proficiency in TCL and Python; experience with libraries, APIs, and data parsing.
- Self-motivated, iterative approach to design, strong engineering judgment, and a bias toward action.
Preferred / Nice-to-have:
- Exposure to power/performance metrics such as TDP, PMAX, EDP, peak and average power.
- Familiarity with power/frequency scaling techniques (DFS, DVFS, AFS, AVFS).
- Experience with power delivery network (PDN) analysis including resonance, Z(f), and voltage droop.
Education Requirements
Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.
About the Company
Company: d-Matrix
Headquarters: Santa Clara, California, United States
d-Matrix is a Santa Clara–based startup developing highly programmable in-memory computing architectures and accompanying software to accelerate generative AI and other AI workloads, focusing on hardware-software co-design for cloud and edge applications.
