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Sr. Staff Physical Design Timing Engineer (STA)

Lightmatter
August 27, 2026
Full-time
Remote friendly (Boston, Massachusetts, United States)
Worldwide
$217,000 - $267,000 USD yearly
Physical Design Jobs, Level - Senior

Job Title

Sr. Staff Physical Design Timing Engineer (STA)

Role Summary

Lead timing analysis and sign-off for Lightmatter's silicon photonics chips across synthesis, place-and-route, and tapeout. Work with architecture, RTL, DFT, methodology, and physical design teams to define timing constraints and achieve timing closure on advanced CMOS nodes.

This role focuses on practical STA execution, timing closure strategy, and automation to enable production-quality tapeouts.

Experience Level

Senior — position expects an experienced engineer (posting cites ~12 years in physical design and a minimum of 5 years hands-on ASIC STA and timing-constraints experience).

Responsibilities

Primary responsibilities include driving STA sign-off and integrating timing flows into chip implementation.

  • Drive STA sign-off for flagship silicon photonics chips across technology nodes.
  • Develop timing constraints and consolidated timing modes for synthesis and PnR flows.
  • Analyze foundry guidelines and incorporate sign-off corners, margins, and derates into timing flows.
  • Perform full-chip STA and project timing summaries across scenarios and corners.
  • Use Tempus/PrimeTime to automate timing ECO generation and support physical implementation.
  • Collaborate with architecture, RTL, and DFT teams to resolve timing complexities.
  • Balance power, performance, and area tradeoffs within implementation flows.
  • Document best practices and lessons learned to improve future projects.

Requirements

Must-have technical skills and experience for immediate impact.

  • Minimum ~12 years of physical design experience; at least 5 years hands-on ASIC STA and timing-constraints development.
  • Proven timing-closure experience with Cadence or Synopsys STA tools (Tempus or PrimeTime).
  • Strong knowledge of on-chip variation derates, multi-mode multi-corner constraints, and clock-tree strategies.
  • Experience from synthesis through place-and-route to tapeout signoff.
  • Scripting proficiency: TCL and Python; familiarity with Perl or shell scripting.
  • Strong analytical and problem-solving skills with attention to detail.
  • Clear, precise communication and ability to work effectively in cross-functional teams.
  • Ability to comply with U.S. export control laws.

Nice-to-have:

  • 8+ years of hands-on ASIC STA and timing-constraints experience noted as preferred by the employer.

Education Requirements

Required: Bachelor's degree in Electrical Engineering or Computer Engineering. Preferred: Master’s degree in Electrical Engineering or Computer Engineering. (The posting did not state an explicit "or equivalent experience" clause.)


About the Company

Company: Lightmatter

Headquarters: Boston, Massachusetts, USA

Lightmatter develops photonic AI data-center infrastructure and optical chips for extreme-scale AI and HPC. The company invented the Passage 3D‑stacked photonics engine to provide high-bandwidth, low-latency interconnects across large-scale processors and raised $400M in Series D financing at a reported $4.4B valuation.

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Date Posted: 2026-08-26