Sr. Staff Physical Design Engineer

Job Title

Senior Staff Physical Design Engineer

Role Summary

Implement and sign off complex digital blocks and full-chip physical implementation for high-performance ASICs at advanced process nodes (3nm). Focus areas include timing closure, power integrity, floorplanning, clock distribution, and physical verification.

Work within a multidisciplinary team developing photonics-enabled systems; role is based in Toronto with a flexible hybrid workplace model.

Experience Level

Senior — 12+ years of industry experience in physical design (per employer qualifications).

Responsibilities

Primary responsibilities span from synthesis through physical verification and signoff for large ASIC designs.

• Implement digital blocks using standard industry flows from synthesis to physical verification.
• Drive full-chip STA signoff: review constraints, debug timing reports, and implement timing ECOs.
• Perform power analysis and optimization while balancing area and performance trade-offs.
• Lead full-chip floorplanning, IO placement, and clock distribution strategy and implementation.
• Customize clock implementations for functional and test clocks; manage clock trees and insertion.
• Debug and resolve DRC/LVS issues and complete physical verification cleanup.
• Implement functional and timing ECOs at block and top level.
• Collaborate with EDA vendors to diagnose and resolve tool issues; automate flows via scripting.
• Write and maintain scripts (TCL, Python, Shell) to automate flows and custom tasks.
• Support manual layout tasks as needed and engage in learning silicon photonics layout when applicable.

Requirements

Must-have technical skills and attributes for immediate contribution.

• 12+ years of industry experience as a Physical Design Engineer on large ASIC or mixed-signal designs.
• Proven track record completing block- or top-level physical design on taped-out chips.
• Thorough knowledge of timing closure methodologies and physical verification flows (DRC/LVS).
• Strong scripting skills (TCL and Python preferred; Shell acceptable) for flow automation and customization.
• Effective collaborator with cross-functional teams and ability to work in a fast-paced environment.
• Ability to comply with applicable export control regulations.

Nice-to-have (preferred):

• Hands-on experience with Cadence EDA tools and industry signoff flows.
• Tape-out experience on 3nm designs and EM/IR analysis using industry signoff tools.
• Experience performing manual layout and willingness to learn silicon photonics layout techniques.

Education Requirements

Required: Bachelor's degree in Electrical Engineering or Computer Engineering. Preferred: Master’s degree in Electrical Engineering or Computer Engineering. (The posting did not state explicit equivalent-experience language beyond the experience requirements.)

About the Company

Company: Lightmatter

Headquarters: Boston, Massachusetts, USA

Lightmatter develops photonic AI data-center infrastructure and optical chips for extreme-scale AI and HPC. The company invented the Passage 3D‑stacked photonics engine to provide high-bandwidth, low-latency interconnects across large-scale processors and raised $400M in Series D financing at a reported $4.4B valuation.