Sr Staff Manager - Physical Design
Marvell TechnologyJob Title
Sr Staff Manager - Physical Design
Role Summary
Technical manager responsible for leading the Physical Design team within Marvell's Data Centre Engineering (Compute & Storage) business unit. Own methodology, automation, and RTL-to-GDSII implementation for complex subsystem partitions and coordinate with SOC, DFT, verification and CAD teams.
Role combines hands-on implementation, technical leadership across multiple projects, and mentoring of senior and junior engineers to deliver timing-closed subsystems for advanced process nodes.
Experience Level
Senior-level manager. The posting requests approximately 15–20 years of related professional experience.
Responsibilities
Lead and execute physical design activities and methodology for complex ASIC subsystems; provide technical direction and coordinate cross-functional delivery.
- Architect and lead development of physical design methodologies and automation flows.
- Provide technical leadership for RTL-to-GDSII tasks: synthesis, floorplanning, place & route, clock tree synthesis, and timing closure.
- Hands-on hardening of complex subsystems and delivery of reference floorplans and timing-closed partition deliverables to the SoC team.
- Coordinate DFT insertion and timing closure at the SoC level with DFT and SoC teams.
- Advise on and resolve complex implementation challenges across multiple projects.
- Collaborate with RTL, verification, CAD, and other cross-functional teams for cohesive execution.
- Mentor and coach senior and junior engineers; promote best practices.
- Evaluate and drive adoption of emerging EDA tools and partner with internal CAD and external vendors.
- Represent the physical design team in strategic technical discussions and roadmap planning.
Requirements
Core technical and managerial qualifications required for the role.
- 15–20 years of professional experience in physical design engineering and team leadership.
- Proven experience with standard RTL-to-GDSII flows and methodology.
- Experience with large, complex designs: synthesis, floorplanning, place & route, clock tree synthesis, and timing closure for subsystems (PCIe, memory, Ethernet, etc.).
- Experience with memory generation and integration.
- Experience with leading foundries and advanced process nodes (for example: 2nm, 3nm, 5nm).
- Strong scripting skills (Perl, Tcl, Python) and strong object-oriented programming ability.
- In-depth understanding of digital logic and computer architecture.
- In-depth knowledge of Verilog and/or VHDL.
- Good communication skills, self-discipline, and the ability to contribute effectively in a team environment.
Education Requirements
Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a related technical field as stated in the posting.
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
