Sr. Staff Front-End ASIC Digital Design Engineer
SynopsysJob Title
Sr. Staff Front-End ASIC Digital Design Engineer
Role Summary
Responsible for front-end RTL development and sign-off for high-performance SoC blocks. Own and deliver RTL from specification through design sign-off, ensuring designs meet lint, CDC/RDC, timing, and power criteria before handoff to physical design.
Work with architects and physical-design teams to meet performance, power, and area targets and to improve front-end methodology and automation.
Experience Level
Senior - typically 8+ years of ASIC design experience with front-end sign-off and STA responsibilities.
Responsibilities
Primary responsibilities include delivering synthesizable RTL, ensuring front-end sign-off quality, and improving methodology and automation.
- Translate architectural specifications and micro-architecture into synthesizable SystemVerilog/Verilog RTL for blocks and subsystems.
- Drive front-end sign-off activities: static timing analysis (PrimeTime), lint, CDC/RDC, synthesis, and power-aware design.
- Develop and review SDC timing constraints; support full-chip timing closure.
- Perform synthesis, QoR analysis, and iterative RTL optimization for area, timing, congestion, and power.
- Apply assertion-based design and formal checks to validate block behavior.
- Run power estimation and analysis and feed findings back into RTL optimization.
- Contribute to methodology improvement, scripting, and regression automation.
Requirements
Must-have technical skills and tools for the role. Education requirements are summarized separately below.
- Proven experience with front-end sign-off flows: STA (PrimeTime), lint (SpyGlass), and CDC/RDC.
- Strong RTL coding skills in SystemVerilog/Verilog for synthesis.
- Experience with synthesis tools and QoR analysis (Design Compiler, Fusion Compiler or equivalent).
- SDC timing constraint development and timing-closure methodology.
- Scripting proficiency in TCL and Python; familiarity with Perl and Linux/UNIX environments.
- Solid digital design fundamentals: FSMs, arbitration, clock-domain crossing, memory interfaces, and AMBA protocols (AXI/AHB/APB).
- Experience with low-power design techniques: clock gating, power gating, multi-Vt, and UPF.
- Nice-to-have: formal verification tools (VC Formal), PrimePower for power analysis, and integration experience with high-speed interfaces (PCIe, DDR/LPDDR, Ethernet, USB, MIPI).
Education Requirements
BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (BS/MS) is specified in the posting. The role also specifies ~8+ years of relevant ASIC design and STA sign-off experience; no explicit "equivalent experience" clause is stated.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
