Sr. Staff Engineer (SystemVerilog & Digital Verification)

Job Title

Sr. Staff Engineer (SystemVerilog & Digital Verification)

Role Summary

On-site engineering role in San Jose within a large RFC/RFIC/DFT organization focused on advanced digital verification for complex SoC and mixed-signal designs. The engineer partners with RTL designers and system architects to define verification strategies and execute block-level and full-chip verification using UVM in SystemVerilog.

Work includes verification of RFID/AMCU integrations, CPU/subsystems, high-speed IO and server interconnects, GNSS-related blocks, and mixed-signal/DMS exposure; emphasis is on practical execution, debugging, and delivery.

Experience Level

Senior — preferred 15+ years of hands-on digital verification experience.

Responsibilities

Main responsibilities:

• Design and build UVM verification environments and testbenches from scratch.
• Develop constrained-random and directed tests and implement functional coverage models.
• Perform deep RTL and protocol-level debugging and root-cause analysis.
• Manage regression suites, run scheduling, and analyze coverage metrics.
• Define verification strategy for block-level and full-chip flows in collaboration with architects and RTL designers.
• Verify interfaces and IPs such as AMBA (AXI/AHB/APB), SPI, UART, JTAG, TileLink, and custom interconnects.
• Support low-power verification techniques (UPF) and integration with mixed-signal verification where required.
• Use and maintain industry EDA tool flows (Cadence tools primarily; VCS/Questa experience beneficial).

Requirements

Minimum and preferred qualifications:

• Must-have: Extensive hands-on experience with SystemVerilog and UVM-based verification, strong RTL debugging skills, and practical SoC verification experience.
• Must-have: Strong understanding of AMBA protocols (AXI, AHB, APB) and other interfaces (SPI, UART, JTAG, TileLink) and CPU/SoC fundamentals including processor architectures, cache coherency, and memory hierarchy.
• Must-have: Experience using Cadence-based EDA flows; familiarity with VCS or Questa is expected.
• Must-have: Proven ability to develop tests, functional coverage, and manage regressions in complex verification environments.
• Nice-to-have: Formal verification exposure, mixed-signal/DMS verification, GNSS or RFID experience, and UPF/low-power verification.
• Other: Strong debugging/problem-solving skills, clear technical communication, and ability to work on-site in San Jose, CA.

Education Requirements

Not specified.

About the Company

Company: Xoriant

Headquarters: Sunnyvale, CA, USA

Product engineering and technology services firm providing software and embedded systems engineering, product development, cloud and digital transformation services for ISVs and enterprises.