Sr Staff Engineer / Staff Engineer / Engineer, Digital Design

Job Title

Sr Staff Engineer / Staff Engineer / Engineer, Digital Design

Role Summary

Design and deliver digital IP and RTL for power-management mixed-signal integrated circuits (PMICs). The role owns digital micro-architecture through silicon delivery, collaborates with analog teams, and drives design-to-silicon correlation for first-pass success.

Works within a cross-functional ASIC/PMIC team to define architecture, implement RTL, support verification and silicon bring-up, and mentor junior engineers.

Experience Level

Mid-level to Senior (3–14 years of relevant digital/mixed-signal ASIC experience). Multiple seniority bands are represented by the job title (Engineer, Staff Engineer, Sr Staff Engineer).

Responsibilities

Core responsibilities focus on architecture, RTL implementation, validation, and team leadership:

• Own digital micro-architecture and develop optimized sub-block architectures for PMICs and intelligent power systems.
• Translate complex requirements into efficient RTL and gate-level netlists; create new IP split between analog and digital.
• Design complex state machines, power sequencers, control loops, and data-processing modules.
• Lead silicon debug, root-cause analysis, and design-to-silicon correlation to achieve first-pass silicon success.
• Perform power-sensitive digital design tasks: power estimation, CDC analysis, and lint flows.
• Implement and analyze digital filters and feedback loops (Z-domain analysis).
• Develop interfaces and controllers (OTP, efuse, memory controllers) and custom low-pin-count high-speed interfaces.
• Collaborate with verification, analog, and validation teams; support qualification and productization.
• Mentor peers and junior engineers; act as a technical leader within the team.

Requirements

Must-have technical skills and experience; listed separately from education requirements.

• 3–14 years of experience in digital design for mixed-signal ICs, with practical PMIC exposure.
• Strong RTL coding skills using Verilog and familiarity with front-end flows.
• Experience with power-sensitive digital design, power estimation, CDC, and lint tools.
• Experience in silicon bring-up, debug, verification, and production readiness.
• Knowledge of communication protocols: I2C, SPI, PMBUS, SVI3, SVID and ability to design custom interfaces.
• Familiarity with OTP/efuse controllers and various memory controller designs.
• Ability to implement and analyze digital filters and control loops (Z-domain familiarity).
• Proven technical leadership, team collaboration, and mentoring capability.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering is required (per posting). No other degrees, certifications, or "equivalent experience" language was specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.