Job Title
Sr Staff Engineer, Physical Design
Role Summary
Lead end-to-end physical design and implementation for chiplet-based MCU SoCs on cost-optimized mature process nodes. Responsible for floorplanning, placement, power planning, routing, timing closure and physical verification while collaborating with architecture, packaging, RTL, verification and test teams to deliver manufacturable, low-power, cost-effective products.
Experience Level
Senior β typically requires 10+ years of ASIC/SoC physical design experience.
Responsibilities
Primary responsibilities include ownership of physical implementation and defining optimized flows for mature-node, chiplet-based designs.
- Own end-to-end physical design: floorplan, placement, power planning, signal integrity, routing, timing closure and sign-off flows.
- Apply mature-node design practices to meet cost and performance targets.
- Implement low-power techniques (clock gating, power gating, leakage reduction) and manage multi-voltage domains.
- Collaborate with architecture, packaging, RTL, verification, DFT and test teams for design convergence and manufacturability.
- Ensure multi-die/chiplet connectivity and compliance with packaging standards for chiplet integration.
- Balance trade-offs among power, timing and area to meet product constraints.
- Define and improve physical design flows; evaluate tools and automation (including AI/ML where applicable) to increase productivity and reduce cost.
Requirements
Must-have technical skills and experience; concise list of required qualifications.
- 10+ years of ASIC/SoC physical design experience with strong focus on low-power and cost-optimized implementations.
- Proven experience with mature-node technologies (for example 12nm, 22nm) and chiplet-based architectures.
- Expertise in Cadence and Synopsys place-and-route tools and sign-off analyses (STA, IR-drop, EM).
- Extensive experience with power-intent methodologies (UPF/CPF) and multi-voltage design flows.
- Strong leadership, cross-functional collaboration and communication skills.
- Nice-to-have: experience with AI/ML in flow development or physical implementation and familiarity with packaging standards for chiplet integration.
Education Requirements
BTech or MTech in Electrical/Electronic Engineering, Computer Engineering or Computer Science. (The posting specifies these degrees.)
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.

Date Posted: 2026-05-20