Sr. Staff Engineer - Digital Design Verification

Job Title

Sr. Staff Engineer - Digital Design Verification

Role Summary

Plan, execute, and own end-to-end digital verification for complex SoCs and subsystems, ensuring production-ready silicon and meeting functional and coverage goals. Work closely with design, architecture, and software teams to close verification gaps and drive tape-outs to successful silicon.

Position is based in Austin, TX and requires onsite presence five days a week.

Experience Level

Senior — 8–12 years of hands-on digital design verification experience.

Responsibilities

Primary responsibilities include verification planning, environment development, SoC-level validation, and driving fixes with design teams.

• Own and execute end-to-end verification at block, subsystem, and full-chip levels.
• Develop verification plans aligned with architecture and design specifications.
• Architect and implement scalable, reusable UVM/SystemVerilog testbenches.
• Create comprehensive test scenarios, stimulus, monitors, checkers, scoreboards, and self-checking mechanisms.
• Perform SoC-level verification using full-chip simulation and regression environments; automate regressions, coverage collection, and reporting.
• Define, track, and close functional and code coverage goals.
• Use advanced debugging and root-cause analysis to isolate and resolve complex design and verification issues; collaborate with design to implement fixes.

Requirements

Key technical and professional requirements. Must-haves are listed first; preferred items follow.

• Must-have: Multiple successful tape-outs with silicon functioning to specification.
• Must-have: Strong experience in block-level, subsystem, and full-chip SoC verification.
• Must-have: Proficiency in SystemVerilog, UVM, and Verilog.
• Must-have: C/C++ based verification experience for SoC-level validation.
• Must-have: Experience with processor-based systems (ARM and/or RISC-V) and AMBA protocols (AXI, AHB, APB).
• Must-have: Ability to define and manage verification deliverables, milestones, schedules, and risk mitigation.
• Must-have: Strong collaboration and communication skills for cross-functional reporting and coordination.
• Nice-to-have: Experience verifying low-power digital architectures and features.
• Nice-to-have: Security IPs (crypto, OTP), DSP/compute subsystems, and edge AI/ML workload enablement.
• Nice-to-have: Scripting and automation skills: Python, Perl, Makefiles.
• Other: Must be currently authorized to work in the United States for any employer.

Education Requirements

BSEE or MSEE (Electrical Engineering) required; 8–12 years of relevant hands-on digital design verification experience specified in the posting. The posting does not cite alternative degrees or explicit "equivalent experience" language.

About the Company

Company: Ambiq

Headquarters: Austin, TX, United States

Semiconductor company developing ultra-low-power microcontroller units (MCUs) and system-on-chip (SoC) platforms for battery-powered and edge devices, focusing on low-power IP, RTL, and production silicon solutions.