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Sr Staff Customer Engineer, Parasitic Extraction

Synopsys
September 19, 2026
Full-time
On-site
Sunnyvale, California, United States
$157,000 - $235,000 USD yearly
EDA Jobs, Level - Senior

Job Title

Sr Staff Customer Engineer, Parasitic Extraction

Role Summary

Serve as the technical lead for parasitic extraction pre-sales and post-sales engagements in North America, focusing on advanced FinFET nodes. Lead benchmarks and proof-of-concept evaluations, manage escalations, and work with sales and R&D to deploy extraction methodologies and expand tool adoption.

Experience Level

Senior - typically 7+ years industry experience (or 5+ years with a Master's degree). Requires demonstrated experience with advanced-node parasitic extraction and customer-facing technical leadership.

Responsibilities

Primary responsibilities include technical benchmarking, customer technical support, escalation ownership, and cross-team collaboration.

  • Lead technical benchmarks and competitive evaluations for interconnect parasitic extraction on advanced FinFET nodes, demonstrating accuracy and performance against customer requirements.
  • Drive pre-sales engagements: methodology presentations, live demos, and proof-of-concept evaluations.
  • Act as primary technical contact for North America accounts on parasitic extraction workflows in digital and custom design flows.
  • Manage customer issues end-to-end: triage, coordinate with R&D, track escalations, and ensure timely closure with clear stakeholder communication.
  • Plan and lead Technical Review and Management Review meetings to align customer roadmaps with solutions and identify expansion opportunities.
  • Collaborate with sales, marketing, and R&D to shape account strategies and influence product direction based on field feedback.
  • Produce technical content: application notes, best-practice guides, and training materials.

Requirements

Must-have technical skills and relevant hands-on experience; optional items listed as nice-to-have.

  • Must-have: Minimum 2 years hands-on experience with interconnect parasitic extraction tools (e.g., StarRC, Quickcap) on advanced FinFET nodes (7nm and below).
  • Must-have: Strong understanding of digital and custom design flows, timing closure, signoff, and reliability analysis.
  • Must-have: Deep knowledge of process technology, design rules, metal stacks, and how these affect extraction accuracy and performance.
  • Must-have: Proficiency in a scripting language (TCL, Perl, or Python) for automation, debugging, and workflow customization.
  • Must-have: Proven ability to run benchmarks, interpret results, and present methodology and findings to technical audiences.
  • Nice-to-have: Experience with commercial static timing analysis tools such as PrimeTime.
  • Nice-to-have: Familiarity with circuit simulation tools such as Hspice or Primesim to correlate extraction results with circuit-level behavior.

Education Requirements

Bachelor's degree in Electrical Engineering or equivalent with 7+ years of industry experience, or Master's degree with 5+ years of experience. Equivalent practical experience is acceptable where stated.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-09-16