Sr. Staff ASIC Verification Engineer

Job Title

Senior Staff ASIC Verification Engineer

Role Summary

Lead all phases of pre-silicon verification for Tensordyne's next-generation AI inference processors, ensuring correctness of computational accelerators integrated with 3rd-party SoC IP. Work closely with design, architecture and lab teams from architecture through tapeout and post-silicon validation.

Experience Level

Senior — expects an experienced engineer. The posting specifies 15+ years of ASIC verification and post-silicon validation experience.

Responsibilities

Accountable for verification planning, implementation, and closure across block, subsystem and full-chip scopes.

• Define verification strategy and lead verification planning from architecture through tapeout.
• Develop block-level, subsystem and full-chip testbenches and tests using object-oriented methodologies (SystemVerilog/UVM).
• Implement constrained-random stimulus, functional coverage, and coverage-driven verification flows; drive coverage convergence.
• Verify SoC/subsystem components including embedded CPUs (ARM/RISC-V) and interconnect subsystems; validate C and assembly diagnostics.
• Triage, debug, and root-cause functional and performance issues; track bugs and manage regression stability.
• Establish reusable verification methodologies and scale testbenches to larger environments.
• Mentor and guide verification engineers through test planning and verification closure.
• Develop scripts and methodologies for front-end ASIC verification flow and perform diagnostic and post-silicon lab validation.

Requirements

Must-have technical skills and experience for the role.

• 15+ years of ASIC verification experience with multiple chips taken through verification and post-silicon validation.
• Expert in SystemVerilog, UVM, constraint randomization, and functional coverage.
• Experience with C/C++ or SystemC for validation and test development.
• Strong understanding of object-oriented programming principles and coverage-driven verification methodology.
• Experience verifying high-speed interfaces (PCIe, Ethernet, DDR/HBM, SerDes, etc.).
• Ability to triage and debug complex functional and performance issues across design and verification environments.
• Excellent communication and leadership skills; experience mentoring engineers and leading verification teams.
• Nice-to-have: scripting experience (Python, Perl, TCL, shell) and interest in AI architectures for convolution/transformer workloads.
• Comfortable working as a self-starter in a fast-paced startup environment.

Education Requirements

B.S. degree in Electrical or Computer Engineering (or similar field) is stated; M.S. is preferred. (No explicit mention of equivalent-experience language.)

About the Company

Company: Tensordyne

Tensordyne is a startup developing high-performance, low-power AI inference processors and multi-chip systems for generative AI acceleration in data centers. The company focuses on ASIC design, verification, and integration of computational accelerators with third-party SoC IP.