Sr. SRAM Layout Design Engineer

Job Title

Sr. SRAM Layout Design Engineer

Role Summary

Lead and execute full custom SRAM and memory macro layout for advanced CMOS process nodes. Work with circuit designers, PnR/integration, CAD, and foundry teams to deliver tapeout-quality memory IP and related physical verification.

Experience Level

Senior — typically 10+ years of relevant custom IC layout experience, with at least 5 years focused on SRAM or memory-IP layout.

Responsibilities

Primary responsibilities include designing, verifying, and delivering memory layouts and improving team layout methodology.

• Manage complete custom layout flow for SRAM bitcells, arrays, periphery, test structures, and memory macros.
• Develop and improve floorplans: array layout, periphery placement, power grid, routing channels, and macro assembly.
• Perform and debug DRC, LVS, ERC, antenna, and other physical verification checks with Calibre, ICV, or equivalent tools.
• Support EM/IR review, power integrity checks, density/fill, dummy insertion, and layout-dependent effects for tapeout readiness.
• Translate schematics into layouts with matching, symmetry, shielding, parasitic targets, and reliability constraints.
• Collaborate with PnR/integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, and power-grid issues.
• Implement and maintain layout methodology, checklists, reusable practices, and quality standards for memory IP delivery.
• Review layouts and mentor junior engineers to raise layout quality and execution rigor.
• Work with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and process constraints.

Requirements

Must-have technical skills, practical experience, and expected behaviors. Nice-to-have items listed separately.

• 10+ years of custom IC layout experience, including at least 5 years in SRAM, memory compiler, or full-custom memory IP layout.
• Hands-on experience in advanced CMOS nodes (FinFET or GAA), preferably at 5nm, 3nm, or smaller.
• Extensive Cadence Virtuoso experience for custom layout creation and review.
• Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
• Proven experience with floorplanning, block-level routing, macro assembly, pin planning, and top-level physical verification.
• Deep understanding of layout-dependent phenomena: LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM concerns.
• Effective cross-team collaboration (circuit build, physical build, integration, CAD, foundry) and clear technical communication.
• Demonstrated ability to mentor junior engineers and enforce quality standards.
• Nice-to-have: knowledge of layout automation or AI-assisted layout tools.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) or equivalent practical experience was specified. Equivalent experience may be accepted in lieu of degree.

About the Company

Company: Oso Semiconductor

Headquarters: Mountain View, CA, United States

Early-stage fabless semiconductor startup developing mmWave beamforming RFICs that deliver 2–4x power reduction for phased array systems across SATCOM, 5G, and radar. Founded by UC Berkeley PhDs, the company has raised Series A funding and works with defense and commercial customers on full-custom mmWave front-end and beamformer chips.