Sr Principal Verification Engineer

Job Title

Sr Principal Verification Engineer

Role Summary

Responsible for designing, developing, and supporting UVM-based verification environments and methodologies for system-level memory/IP models used with hardware-based verification products. Role includes planning verification effort, executing complex protocol and subsystem verification, and integrating coverage, reporting, and regression processes.

Experience Level

Senior — position level Principal (T4). Typically requires about 5–7+ years of relevant verification experience.

Responsibilities

Key responsibilities focus on functional verification of IP and subsystems, environment development, and process integration.

• Plan and execute complex verification projects from requirements through delivery and post-delivery support.
• Design, develop, update, and maintain UVM-based verification environments for memory and protocol IP.
• Analyze customer and vendor protocol specifications and translate into verification requirements and tests.
• Integrate tools and processes for coverage collection, reporting, regression, and automation.
• Research and prototype tools, languages, and methodologies to improve verification effectiveness.
• Support product regression, OS compliance, automation, and release preparation.
• Mentor junior engineers and collaborate across functions and geographies.

Requirements

Must-have technical skills and experience; recommendations are listed separately.

• Expert knowledge of HDLs/HVLs (Verilog, SystemVerilog) and experience with simulation/emulation flows.
• Deep experience with UVM and SystemVerilog testbench development; strong C++ skills for verification infrastructure.
• Proven experience debugging design and verification issues using commercial EDA tools.
• Practical experience verifying protocol-based blocks and SoC-level functional verification.
• Experience with multiple protocols such as SDRAM (LPDDRx, DDRx, HBMx), DFI PHY, UFS/Unipro/MPHY, Ethernet, PCIe, USB3/4, MIPI, or similar.
• Experience designing and implementing complex verification environments and testbenches.
• Experience in process automation and scripting to support regression and tool flows.
• Strong written and verbal English; ability to collaborate with customers, vendors, and cross-functional teams.

Education Requirements

BS or MS in Electrical Engineering, Electronics, or Computer Science. Role expects approximately 5–7+ years of relevant verification experience (Principal/T4 level).

Additional Qualifications / Nice-to-have

Preferred skills that strengthen a candidate's fit.

• Experience using Cadence simulation and/or emulation products.
• Experience in memory sub-system or memory controller verification and operation.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.