Sr. Principal Engineer, RTL ASIC Design
Marvell TechnologyJob Title
Sr. Principal Engineer, RTL ASIC Design
Role Summary
Lead SoC and RTL design for advanced, high-complexity ASICs. The role defines micro-architecture and register specifications, implements RTL, and drives cross-functional reviews with architecture, verification, physical design, firmware, and customers.
Work with global teams and third-party IP vendors to deliver production-quality SoCs from specification through pre-silicon verification and implementation readiness.
Experience Level
Senior. Typical experience guidance from the posting: 18+ years for candidates with a Bachelor's or Master's degree; 16+ years for candidates with a PhD.
Responsibilities
Core responsibilities include defining architecture and implementing RTL while coordinating with multiple engineering disciplines.
- Define SoC and subsystem architecture, micro-architecture, and register specifications for complex SoCs.
- Translate specifications into RTL using coding best practices and industry-standard HDLs.
- Lead cross-functional design and architecture reviews with system architects, IP vendors, and customers.
- Collaborate with physical design teams on floorplanning, power analysis, synthesis guidance, and timing closure support.
- Work with verification teams on pre-silicon verification plans, coverage, full-chip simulation and emulation, and debug.
- Specify and define customization requirements for third-party IP (controllers, PHYs, etc.).
- Perform performance, area, power, and security trade-off analyses and optimize designs accordingly.
- Contribute to development and evaluation of design and verification methodologies.
Requirements
Key technical skills and experience required. (Degrees and formal education requirements are listed separately below.)
- Must-have:
- Proven SoC architecture and HW micro-architecture design experience for complex SoCs.
- Strong RTL design skills in HDL (SystemVerilog/Verilog) and RTL implementation best practices.
- Experience with ARM-based SoC architectures, memory management, and virtualization concepts.
- Hands-on experience with high-speed interfaces and interconnects (PCIe, CXL, DDR) and system cache design.
- Experience with performance analysis, simulation, modeling, and VLSI implementation flow (synthesis, timing, power analysis).
- Proficiency in scripting and automation for design and verification flows (e.g., Python, Tcl, Perl).
- Strong communication and collaboration skills for working with global teams, customers, and IP vendors.
- Nice-to-have:
- Experience with full-chip emulation/simulation platforms, coverage analysis, and debug at scale.
- Prior work defining customization for third-party IP and deep involvement in floorplanning and power/quality-of-service trade-offs.
Education Requirements
Posting specifies a Bachelor's or Master's degree in Computer Science, Electrical Engineering, or related fields (with 18+ years of experience), or a PhD in those fields (with 16+ years of experience). Fields named: Computer Science and Electrical Engineering. No alternative "equivalent experience" language was provided explicitly.
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
