Sr Principal Digital Engineer
RenesasRole Summary
The Sr Principal Digital Engineer will be responsible for timing design and timing analysis for automotive SoCs, focusing on integrating various technology elements needed for high-performance vehicle systems. This role involves designing timing constraints and ensuring quality checks before releasing to production.
Experience Level
Senior level. Experience in LSI design and timing analysis required.
Responsibilities
The key responsibilities include:
- Developing the SoC timing design strategy.
- Creating and verifying timing constraints (SDC).
- Evaluating and implementing new toolsets and design flows.
Requirements
Must-have skills include:
- Experience in timing design and LSI design using synthesis tools.
- Knowledge of SDC development and quality checking using timing analysis tools.
- Development experience using scripting languages like Python or Tcl.
- Ability to communicate effectively in English.
Nice-to-have skills:
- Familiarity with CPU, GPU, image IP, buses, and memory controllers related to SoCs.
Education Requirements
Not specified.
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
