Sr. Principal Design Verification Engineer (PCIe/CXL)

Job Title

Sr. Principal Design Verification Engineer (PCIe/CXL)

Role Summary

Lead verification engineer responsible for planning, architecting, and executing design verification for PCIe/CXL subsystems within Marvell Data Centre Engineering (Compute & Storage). The role focuses on defining DV processes, creating test plans and testbenches, driving coverage closure, and coordinating verification activities across IP, subsystem, and SoC teams.

Experience Level

Senior — 18+ years of relevant experience.

Responsibilities

The role owns end-to-end verification delivery for PCIe/CXL subsystems and ensures designs meet functional and performance requirements through simulation, emulation, and post-silicon collaboration.

• Define and improve DV processes for efficient, high-quality verification execution.
• Lead end-to-end PCIe/CXL subsystem DV execution and sign-off.
• Collaborate with IP, Subsystem, and SoC teams on test plan creation, testbench architecture, and milestone reviews.
• Architect and implement simulation testbenches using UVM and C; develop BFMs, scoreboards, monitors, and verification components.
• Develop and execute test plans to verify design correctness and performance; drive coverage closure and gate-level simulations.
• Coordinate with Architecture, Chip Lead, Emulation, Program Management, and other cross-functional teams to drive subsystem-level DV execution.
• Partner with silicon bring-up and firmware teams to support post-silicon validation and bring-up.
• Own and debug simulation failures to identify and resolve root causes.

Requirements

Must-have technical skills and experience required to perform the role:

• Proven experience leading core technical project deliveries in design verification at the subsystem level (PCIe/CXL).
• Strong UVM experience: coding subsystem/block-level testbenches, BFMs, scoreboards, monitors, and verification environments.
• Proficient writing and debugging tests in UVM and in C.
• Experience with industry standard interfaces such as PCIe and CXL.
• Knowledge of ARM architecture and AMBA bus standards (AXI-4, CHI, ACE).
• Experience with verification toolflows from Cadence, Synopsys, Mentor and/or ARM verification tools.
• Proficient in scripting (tcl, Perl) and familiar with version control tools (GIT, SVN).
• May require eligibility to access export-controlled technology; candidates may be subject to export license review.

Nice-to-have:

• Experience with assertion-based formal verification tools.
• Experience with hardware emulation and emulation support.

Education Requirements

Master's or Bachelor's degree (stated) with 18+ years of relevant experience. No specific field of study was listed; equivalent practical experience was not specified explicitly.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.