Sr Principal Design Engineer (Chiplet Solutions)

Job Title

Sr Principal Design Engineer (Chiplet Solutions)

Role Summary

Lead front-end engineering for Cadence Silicon Solutions Group (SSG) to develop and integrate IP and chiplet subsystems for high-performance markets. Based in Edinburgh and working with global chiplet teams across Europe, India and the USA.

Responsible for hands-on RTL and verification leadership, defining chiplet architecture, driving quality assurance flows, planning development milestones, and engaging with customers and cross-functional domain leads.

Experience Level

Senior — requires 12+ years' experience in the microelectronics/EDA industry with proven technical leadership.

Responsibilities

Provide technical leadership and hands-on execution across chiplet IP development, integration, and delivery.

• Technical leadership of complex silicon programs and leading-edge IP.
• Collaborate with chiplet architecture team to define next-generation chiplets.
• Integrate Cadence IP (e.g., UCIe, PCIe, Ethernet, USB, NPU, Audio, Vision) and partner IP (CPUs, ISP, NoCs, silicon monitors).
• Hands-on leadership of RTL, testbench, formal analysis and trial synthesis activities.
• Implement quality assurance via hierarchical LINT, CDC analysis and release flows.
• Plan activities, schedules and milestones for chiplet subsystems and system IP development.
• Lead cross-functional technical meetings with verification, software and other domain leads.
• Support customer pre-sales and post-sales technical engagements.
• Participate in technical review meetings and ISO-9001 checklist reviews.
• Represent the company at industry conferences and technical forums; travel typically under 10%.

Requirements

Key technical skills and experience required; preferences noted separately.

• Verilog RTL design experience (essential).
• Metric Driven Verification (MDV) experience (essential).
• Experience with front-end tools and flows: LINT, synthesis and CDC analysis (essential).
• SoC architecture and development experience (essential).
• Proven technical team leadership and program planning skills (essential).
• Excellent written and spoken English; strong interpersonal and communication skills.
• Self-motivated with strong organizational and collaboration abilities.
• Nice-to-have: experience with AMBA, PCIe, CXL, UCIe protocols; familiarity with quality processes such as ISO-9001 and ISO-26262.

Education Requirements

Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline. (The posting specifies a degree but does not state the exact level such as Bachelor's/Master's, nor does it state an explicit "or equivalent experience" clause.)

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.