Sr Principal Design Engineer

Job Title

Sr Principal Design Engineer

Role Summary

Design, develop, verify, and support system-level memory IP models for hardware-based verification platforms. The role is an individual-contributor position that works closely with internal teams and external customers to deliver production-quality memory models across multiple memory technologies and interfaces.

This work supports verification of complex SoCs and memory subsystems used in simulation and emulation environments.

Experience Level

Senior-level. Typically requires 5+ years of experience designing complex protocols, RTL, and hardware systems.

Responsibilities

Primary responsibilities include designing and maintaining memory IP models, verifying RTL, debugging system issues, and supporting customers and cross-functional teams.

• Design, develop, verify, and productize system-level memory IP models for hardware-based verification platforms.
• Implement memory models for technologies such as LPDDR, HBM, NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS.
• Write high-quality RTL using Verilog/SystemVerilog and follow sound design/coding practices.
• Develop and execute verification strategies using simulation and emulation tools and methodologies.
• Diagnose and resolve complex RTL, protocol, system, and customer issues via debugging and root-cause analysis.
• Create and maintain design specifications, user documentation, and product support materials.
• Work directly with internal and external customers to gather requirements and resolve issues in verification environments.
• Plan and manage project schedules, priorities, and deliverables while adapting to changing customer needs.
• Collaborate with cross-functional teams to enable cross-verification, knowledge sharing, and product improvements.

Requirements

Must-have technical skills, experience, and professional abilities.

• Extensive hands-on experience with Verilog/SystemVerilog RTL design.
• Strong understanding of RTL verification methodologies, tools, and flows.
• Proven ability to debug complex hardware, RTL, protocol, and system-level issues.
• Experience developing and executing verification strategies on simulation and emulation platforms.
• Strong analytical, problem-solving, and organizational skills; ability to manage multiple priorities.
• Excellent written and verbal communication skills in English and ability to work directly with customers.
• Ability to work effectively as an individual contributor and collaborate across engineering and product teams.
• High emotional intelligence and a collaborative approach to communication and conflict resolution.

Nice-to-have

• Experience with Cadence simulation and/or emulation products.
• Familiarity with hardware emulation or other hardware-based verification platforms.
• Programming or scripting experience (Perl, Tcl/Tk, C-shell, or similar).
• Experience with memory subsystem architecture and developing reusable IP models or verification components.

Education Requirements

Master of Science in Electrical Engineering (MSEE) or equivalent advanced degree (MS/PhD) is specified. The role also expects a minimum of 5 years of significant experience designing complex protocols, RTL, and/or hardware systems.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.