Sr Principal Application Engineer

Job Title

Sr Principal Application Engineer

Role Summary

Technical leader responsible for driving customer success for AI-enabled digital implementation and timing signoff workflows using Innovus and related Cadence platforms. The role combines hands-on backend physical-design expertise with adoption and deployment of AI/data-driven automation across customer flows.

Work involves direct customer engagement, pre- and post-sales technical support, cross-team coordination (AE, PE, R&D), and development of scalable workflows and best practices for large-scale SoC implementation and signoff.

Experience Level

Senior-level. Title indicates a principal/senior role; specific years of experience are not stated in the posting.

Responsibilities

Primary responsibilities focus on enabling AI-driven implementation/signoff workflows, supporting customers, and improving physical-design closure and signoff processes.

• Lead adoption and deployment of AI-driven design and debug workflows (e.g., AI assistants and multi-agent flows).
• Develop and apply AI/ML or data-driven techniques to automate flows, speed debug, and improve design convergence.
• Act as a trusted technical advisor to key customers; deliver workshops, training, and best-practice guidance.
• Drive issue resolution across AE, PE, and R&D teams and build long-term customer relationships.
• Drive end-to-end physical design closure: floorplan, placement, CTS, routing, optimization, congestion and power tuning.
• Debug complex block and full-chip issues; provide scalable solutions to improve PPA and turnaround time.
• Enable timing closure and signoff flows; debug setup/hold violations and multi-mode/multi-corner issues.
• Contribute to internal and customer-facing initiatives for next-generation implementation and signoff methodologies.

Requirements

Must-have technical skills and experience required to perform the role.

• Proven experience in one or more of: AI/ML or data-driven workflows applied to engineering, digital backend design (physical design / PnR), or EDA application engineering/CAD support.
• Strong technical foundation in place-and-route (PnR) flows and/or static timing analysis (STA) and timing-closure methodologies.
• Hands-on experience with Innovus or comparable implementation tools.
• Strong debugging and problem-solving skills in complex SoC designs.
• Effective written and verbal communication skills for customer-facing activities.

Nice-to-have:

• Experience applying AI/ML in EDA (AI-assisted debug, workflow automation, data-driven optimization).
• Experience with advanced process nodes (≤7nm) and large-scale SoC/full-chip implementations.
• Familiarity with timing signoff methodologies (MMMC, variation modeling, extraction and correlation flows) and other Cadence tools (Tempus, Quantus, Pegasus, Genus).
• Prior application engineering, CAD, or customer-facing role experience.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related technical field (as listed in the posting).

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.