Sr. Physical Design Engineer, Annapurna Labs

Job Title

Sr. Physical Design Engineer, Annapurna Labs

Role Summary

Join the Cloud-Scale Machine Learning Acceleration team to design and optimize custom SoCs used in AWS machine learning servers (inference and training). The role focuses on physical implementation and sign-off for large-scale datacenter silicon.

This position is part of Annapurna Labs within AWS and requires close collaboration with RTL, architecture, and verification teams to deliver production-quality chips.

Experience Level

Senior — experienced ASIC physical design engineer. The role expects multi-year senior-level experience in physical design and sign-off.

Responsibilities

Key responsibilities include:

• Collaborate with RTL and architecture teams to assess feasibility and PPA trade-offs.
• Drive physical implementation of IO/core subsystems and blocks: synthesis, floorplanning, pin/bus planning, place & route, and ECOs.
• Perform power and clock distribution design, congestion and timing analysis, IR drop analysis, and physical verification to sign-off quality.
• Develop and refine physical design methodologies and flows.
• Evaluate and integrate 3rd-party IP; define and drive IP physical requirements.
• Contribute to team practices through collaboration, mentoring, and knowledge sharing.

Requirements

Must-have technical skills and experience:

• 6+ years of ASIC physical design experience (RTL-to-GDSII) including work at advanced nodes (examples: 7nm, 14/16nm, 20nm, or 28nm).
• Proven hands-on experience across the physical design flow: synthesis, floorplanning, place & route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO.
• Experience with commercial EDA tools (Cadence, Mentor Graphics, Synopsys, or equivalent) for physical implementation and sign-off.
• Experience scripting for automation and flow development (Python, Perl, Bash, or PowerShell).
• Deep understanding of sign-off activities (timing, IR/EM, physical verification).

Nice-to-have:

• Experience mentoring or leading junior engineers.
• IP integration experience and ability to specify and drive physical IP requirements.
• Familiarity with device physics, custom/semi-custom implementation techniques, and system interfaces (DDR, PCIe, fabrics).
• Experience extracting design parameters and QOR metrics and performing trend analysis.

Education Requirements

Required: Bachelor of Science in Electrical Engineering or Computer Science plus 8 years of relevant experience, OR Master of Science in Electrical Engineering or Computer Science plus 6 years of relevant experience (as stated in the posting).

Compensation & Additional Information

Base salary ranges reported in posting:

• Cupertino, CA: 183,000 - 247,600 USD annually
• Austin, TX: 159,200 - 215,300 USD annually

Company: Annapurna Labs (U.S.) Inc. Job ID: A10409016.

Amazon is an equal opportunity employer. Accommodation information is available through Amazon recruiting resources.

About the Company

Company: Amazon Web Services

Headquarters: Seattle, Washington, USA

Amazon Web Services (AWS) provides a comprehensive and evolving cloud computing platform that includes infrastructure as a service (IaaS), platform as a service (PaaS), and software as a service (SaaS). AWS allows business and developers to use a wide range of cloud services for computing power, storage, and content delivery, among others, thus fostering innovation and enabling faster deployment of applications. AWS is designed to be scalable, flexible, and cost-effective across industries worldwide.