Sr. Physical Design Engineer, Annapurna Labs

Job Title

Sr. Physical Design Engineer, Annapurna Labs

Role Summary

Join the Cloud-Scale Machine Learning Acceleration team to design and optimize custom SoCs used in AWS ML servers (Inferentia, Trainium). The role focuses on ASIC physical implementation, driving block- and chip-level physical design closure and developing practical methodologies for high-quality silicon delivery.

Experience Level

Senior-level. Typically requires multi-year ASIC physical design experience (see Requirements for details).

Responsibilities

The engineer will execute and lead physical implementation tasks and collaborate with RTL/architecture teams to meet performance, power, area, and schedule goals.

• Collaborate with RTL and logic designers to assess architectural feasibility and PPA tradeoffs.
• Drive IO/core subsystem and block physical implementation: synthesis, floorplanning, bus/pin planning, place & route, power/clock distribution, congestion and timing closure, IR drop analysis, ECO and sign-off.
• Perform congestion, timing, and IR drop analysis and resolve closure issues through design or flow changes.
• Develop and improve physical design methodologies and flows for production use.
• Evaluate third-party IP and specify physical-domain IP requirements.
• Work closely with other physical design engineers and cross-functional teams to integrate designs at server scale.

Requirements

Must-have skills and experience for effective performance in this role.

• 6+ years of ASIC physical design experience (RTL-to-GDSII), including block design and chip integration.
• Proven experience using mainstream EDA tools (examples: Cadence, Synopsys, Mentor) across synthesis, equivalency checks, floorplanning, place & route, power/clock distribution, and physical verification.
• Hands-on experience with timing closure, congestion analysis, IR drop/EM analysis, and ECO implementation.
• Scripting experience (Python, Perl, Bash, or PowerShell) to automate flows and tasks.
• Deep understanding of sign-off activities: timing sign-off, IR/EM, and physical verification.

Nice-to-have / preferred:

• Experience mentoring or leading junior engineers.
• Ability to develop CAD tool flows for synthesis, formal checks, floorplanning, and P&R automation.
• Experience integrating IP and driving IP requirements in the physical domain (multi-year background).
• Familiarity with device physics, custom/semi-custom implementation techniques, and interfaces/technologies such as DDR or PCIe.
• Experience extracting design parameters, QOR metrics, and analyzing trends to guide design decisions.

Education Requirements

BS + 8 years or MS + 6 years in Electrical Engineering, Computer Science, or a closely related technical field (as listed in the posting). No certifications specified.

About the Company

Company: KGS

KGS is a government and commercial contracting firm that provides engineering, technical, and staffing solutions, often supporting aerospace, defense, and IT projects for federal and industry customers.