Senior / Staff / Sr. Staff Engineer - Design Verification

Job Title

Senior / Staff / Sr. Staff Engineer - Design Verification

Role Summary

Lead verification strategy, methodology, and execution for out-of-order (OOO) CPU core blocks. Own verification plans, drive coverage and sign-off, and provide technical leadership and mentoring within the design verification (DV) team.

Experience Level

Senior — typically 5+ years of relevant verification or RTL experience.

Responsibilities

The role focuses on establishing and delivering verification for complex OOO CPU subsystems and on mentoring the DV team.

• Own DV for major OOO core subsystems (front-end, rename/register mapping, issue queues/schedulers, execution units, ROB/retirement, LSU, L1 caches, TLBs, MMU/coherence interfaces).
• Translate ISA and micro-architecture specifications into detailed verification plans and test strategies.
• Architect and implement SystemVerilog/UVM testbenches, reusable UVM environments, agents, monitors, scoreboards, and reference models.
• Design constrained-random and targeted stimulus for OOO corner cases (deep speculation, hazard patterns, reorder stress).
• Define and evolve DV methodology and scenario libraries for speculation, memory ordering, and multi-core interactions; promote reuse across projects.
• Define coverage models and sign-off criteria (functional, code, assertion, and scenario coverage) and drive coverage closure for owned blocks.
• Develop and maintain assertion sets (SVA) for key OOO properties and verify correctness of recovery, ordering, forwarding, and replay behaviors.
• Lead debug of complex functional failures, memory ordering/coherence issues, and TLB/MMU corner cases; collaborate with RTL, micro-arch, performance, and post-silicon teams.
• Mentor junior and mid-level DV engineers and lead DV design/reviews and verification-related architecture reviews.

Requirements

Must-have technical skills and experience for immediate contribution.

• Proven experience verifying complex out-of-order CPU cores and subsystems (front-end, ROB, LSU, caches, TLBs, coherence).
• Strong SystemVerilog and UVM experience; ability to architect reusable testbenches and verification environments.
• Experience with coverage-driven verification, coverage closure, and developing coverage models.
• Experience writing and maintaining assertions (SVA) for micro-architectural properties.
• Skilled in constrained-random stimulus, directed tests for corner cases, and building scenario libraries for speculation and memory ordering.
• Demonstrated debug skills for subtle OOO failures and multi-core memory/coherence bugs.
• Experience collaborating closely with micro-architecture, RTL, performance, and post-silicon teams.
• Proven ability to mentor engineers and lead verification efforts across projects.
• Strong communication skills and experience participating in architecture and design reviews.
• Nice-to-have: experience with post-silicon validation, performance modeling, or formal verification techniques.

Education Requirements

Bachelor's or Master's degree in Engineering. The posting specifies 5+ years of experience; candidates with equivalent practical experience may be considered. (Degree and years of experience were stated in the source.)

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.