Sr. Physical Design Engineer, Annapurna Labs

Job Title

Sr. Physical Design Engineer, Annapurna Labs

Role Summary

Join the Cloud-Scale Machine Learning Acceleration team to design and optimize custom SoCs used in AWS ML servers (Inferentia, Trainium). The role focuses on RTL-to-GDSII physical implementation, sign-off activities, and developing physical design methodologies for datacenter-class ASICs.

Experience Level

Senior — requires substantial hands-on ASIC physical design experience (senior-level individual contributor).

Responsibilities

Primary responsibilities center on physical implementation, quality, and collaboration with architecture and RTL teams.

• Collaborate with RTL/logic designers to assess architectural feasibility and PPA trade-offs.
• Drive IO/core subsystem and block physical implementation including synthesis, floorplanning, pin/bus planning, place-and-route, and ECO.
• Perform power and clock distribution design, congestion analysis, timing closure, IR drop/EM analysis, and physical verification through sign-off.
• Develop and improve physical design methodologies and flows.
• Evaluate third-party IP and define physical-domain IP requirements and integration strategy.
• Work cross-functionally to resolve physical-design issues and support design sign-off.

Requirements

Must-have technical skills and domain experience.

• 6+ years in ASIC physical design (RTL-to-GDSII) with block-level implementation experience using modern process nodes (examples listed: 7nm, 14/16nm, 20nm, 28nm).
• Hands-on experience with EDA tool flows for synthesis, equivalency verification, floorplanning, place-and-route, timing closure, power/clock distribution, congestion analysis, IR drop analysis, physical verification, and ECO (Cadence, Synopsys, Mentor, or similar).
• Deep understanding of sign-off activities (timing, IR/EM, physical verification).
• Scripting proficiency (Python, Perl, Bash, or PowerShell) to automate flows and analyses.
• Strong collaboration and communication skills to work with RTL, architecture, and verification teams.

Nice-to-have:

• Experience mentoring or leading junior engineers.
• Experience developing CAD/EDA flows and automation for synthesis, floorplanning, P&R, sign-off.
• 4+ years integrating third-party IP and specifying IP requirements for the physical domain.
• Knowledge of device physics, custom/semi-custom implementation techniques, and high-speed interfaces (DDR, PCIe, fabrics).
• Experience extracting QOR metrics and analyzing design parameter trends.

Education Requirements

Bachelor of Science (BS) plus 8 years of relevant experience, or Master of Science (MS) plus 6 years, in Electrical Engineering (EE) or Computer Science (CS).

About the Company

Company: KGS

KGS is a government and commercial contracting firm that provides engineering, technical, and staffing solutions, often supporting aerospace, defense, and IT projects for federal and industry customers.