Sr Physical Design Engineer

Job Title

Sr Physical Design Engineer

Role Summary

Senior engineer responsible for physical verification (PV) and power integrity signoff for block and full-chip digital, analog, and mixed-signal designs. The role drives PV signoff activities, EM/IR analysis, and methodology automation to ensure tapeout readiness.

Works with layout, circuit, package, CAD/EDA and foundry teams to resolve violations, implement foundry rule updates, and improve PV/EMIR productivity and reliability.

Experience Level

Senior / Experienced. The posting specifies an experienced level but does not list a specific years-of-experience range.

Responsibilities

Primary responsibilities include PV signoff, EM/IR analysis, and methodology development.

• Own and drive full-chip and block-level PV signoff activities and documentation for tapeout readiness.
• Perform and debug DRC, LVS, parasitic extraction (PEX), PERC/ERC, antenna checks, density and DFM checks.
• Analyze and resolve complex PV violations while meeting schedule commitments; review and implement foundry rule deck updates.
• Perform Electromigration (EM) and IR drop analysis; define power integrity verification strategies and recommend corrective actions.
• Develop automation, scripts, dashboards, and reporting for PV and EM/IR flows to improve productivity and metrics visibility.
• Collaborate with layout, circuit, package, PD, CAD/EDA, and foundry support teams; participate in design and signoff reviews and tapeout planning.
• Mentor junior engineers and provide technical guidance on PV and power-integrity topics.

Requirements

Must-have technical skills and experience; where possible items are practical requirements for the role.

• Proven experience with PV signoff including DRC, LVS, PEX, PERC/ERC, antenna checks, and DFM flows.
• Experience performing EM and IR drop analysis and defining power integrity strategies for block and full-chip designs.
• Proficiency in scripting and automation using Python, Tcl, Shell, or SKILL to build and maintain PV/EMIR flows.
• Experience working with foundry rule decks, layout and design teams, and CAD/EDA tool flows to achieve signoff.
• Ability to debug complex verification and reliability issues and close signoff requirements before tapeout.
• Willingness to travel up to ~10% and to support first-shift/daytime schedules.

Education Requirements

Not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.