Sr. Packaging Engineer (Semiconductor)

Job Title

Sr. Packaging Engineer (Semiconductor)

Role Summary

Lead development and qualification of advanced semiconductor package architectures for discrete protection products (TVS, TDS, Hot Switch). Partner with OSATs, IC design, process, product engineering, and test teams to deliver manufacturable, reliable packages that meet electrical, thermal, and mechanical requirements.

Experience Level

Senior; typically requires 5+ years of progressive semiconductor packaging engineering experience.

Responsibilities

Primary responsibilities include package design, qualification, and manufacturing support across the product lifecycle.

• Define, develop, and qualify advanced package architectures (WLCSP, DFN, QFN, flip‑chip, multi‑die) to meet electrical, thermal, and mechanical targets.
• Serve as technical interface to OSAT partners for process capability improvements, design rule enforcement, and supplier qualification.
• Plan and execute package-level reliability qualification per JEDEC and AEC‑Q101 (HTSL, HAST, TC, MSL) and support root-cause investigations.
• Perform failure analysis for package-related defects (die cracking, chipping, delamination, wire bond lift, interconnect degradation) and drive corrective actions to improve yield.
• Collaborate with IC design, process engineering, product engineering, and test teams to ensure package constraints and parasitics are addressed early.
• Conduct package-level electrical and thermal simulations and validate results through characterization and bench testing.
• Contribute to the advanced packaging technology roadmap by identifying emerging technologies, material innovations, and cost-reduction opportunities.
• Author and maintain packaging specifications, process control documents, design rule guidelines, and qualification reports to ensure traceability and compliance.

Requirements

Must-have technical skills and experience for immediate impact; preferred items noted where applicable.

• Minimum 5 years of semiconductor packaging engineering experience with demonstrated technical responsibility.
• Hands-on experience with WLCSP, DFN, QFN, SOD, SOT, and flip‑chip assemblies for discrete protection devices.
• Direct experience working with OSAT partners on process development, design rule definition, and supplier qualification.
• Proven ability to execute JEDEC and AEC‑Q101 reliability qualification programs, including test plan development and formal reporting.
• Deep knowledge of assembly processes: wafer dicing, die attach, wire bonding, molding, plating; and wafer-level packaging processes (WBC, CDAF).
• Proficiency in failure analysis techniques: cross-sectioning, SEM/EDX, SAT (scanning acoustic tomography), and optical microscopy.
• Working knowledge of package-level electrical and thermal simulation tools and familiarity with SPC, CPK analysis, and DOE methodologies.
• Understanding of ESD/TVS device physics and the impact of package parasitics on transient protection performance.
• Strong technical communication skills, ability to work in global cross-functional teams, and willingness to travel to OSAT/fab partner sites.

Education Requirements

Bachelor's degree required in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, or a closely related field. Master's degree or PhD preferred.

About the Company

Company: Semtech

Headquarters: Camarillo, California, USA

Semtech Corporation is a high-performance semiconductor company providing IoT systems and Cloud connectivity solutions. The company focuses on delivering innovative technology solutions that support a smarter, more connected, and sustainable planet, with a dedication to quality across infrastructure, industrial, and consumer markets.