Sr. Memory Validation Engineer

Job Title

Sr. Memory Validation Engineer

Role Summary

Owner of the data and automation layer for the memory subsystem on Ambarella ASICs. This role combines hands-on silicon bring-up and failure debug with development of automation and analysis pipelines that improve memory training, calibration, and long-term reliability.

The engineer will work with lab, field, and validation teams to detect instability early, convert data into actionable insight, and influence future memory controller designs.

Experience Level

Senior-level. Guidance: 4+ years in memory validation, memory controller design, SoC validation, or a closely related area.

Responsibilities

Primary responsibilities focus on memory training, automation, data-driven validation, and supporting silicon readiness.

• Develop, maintain, and tune memory training and calibration code for LPDDR5/5X and LPDDR6 to ensure reliable operation across parts, boards, and conditions.
• Collect, aggregate, and analyze memory subsystem data from lab testing, customer platforms, and internal validation systems.
• Build automation for stability testing, performance characterization, speed binning, and regression analysis to expand coverage and reduce cycle time.
• Debug customer and field issues, drive investigations from initial report to root cause and closure.
• Translate failure analysis and system behavior into design and validation improvements for memory controllers.
• Validate power-saving features and characterize tradeoffs between performance, reliability, and power across real-world use cases.
• Support silicon bring-up, qualification, and production readiness for memory subsystems.

Requirements

Must-have skills and experience required to perform the role.

• 4+ years in memory validation, memory controller design, SoC validation, or closely related area.
• Hands-on experience with LPDDR5/5X and LPDDR6 and familiarity with relevant JEDEC specifications.
• Experience owning or contributing to memory training and calibration code; C/firmware skills to maintain those routines.
• Strong Python (or equivalent) skills for test automation and data analysis.
• Practical hardware debug skills: bench instrumentation, protocol and logic analyzers, boot and stability failure triage.
• Ability to work directly with customers and cross-functional teams under time pressure.

Nice-to-have:

• Silicon bring-up or post-silicon validation experience on a production program.
• Signal integrity fundamentals: eye diagrams, jitter, and timing margin analysis on high-speed interfaces.
• Experience validating low-power states (self-refresh, power-down, DVFS-style transitions).
• Statistical analysis, machine learning, or dashboarding applied to hardware validation data.
• Firmware or driver-level exposure to the memory stack.

Education Requirements

Not specified.

About the Company

Company: Ambarella

Headquarters: Santa Clara, California, USA

Ambarella is a leader in computer vision and video processing technology, providing advanced solutions that enhance the performance of video applications. Focused on quality and innovation, Ambarella develops products for diverse uses, including autonomous vehicles, surveillance systems, and smart cameras, aiming to deliver pristine imagery and efficient compression while minimizing power consumption.