Sr. Manager, Silicon Design Engineering
Lead static timing analysis (STA) and clocking strategy for complex SoC and IP designs, including chiplet and 3D stack interfaces. Drive timing-closure methodologies, collaborate with IP, domain, CAD and methodology teams, and ensure delivery of high-performance, power-efficient silicon.
Role includes people management; remote work is permitted.
Senior. Typically requires a Master’s plus 4 years of relevant experience, or a Bachelor’s plus 6 years of relevant experience in silicon or ASIC physical design/STA and engineering leadership.
Primary responsibilities include technical leadership for STA and timing closure, architectural analysis, and cross-functional coordination.
Must-have technical skills and experience (non-exhaustive):
Master’s degree in Electronics Engineering, Computer Science, Computer Engineering, Electrical Engineering, or a related field is required; employer will alternatively accept a Bachelor’s degree in those fields plus six years of relevant experience. Foreign equivalents are acceptable.
Company: Advanced Micro Devices
Headquarters: Sunnyvale, California, USA
Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.
